From 21f1fd95dbc8c84c770f38fec558d18c66249da7 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Fri, 18 Sep 2015 11:21:22 +0530 Subject: Tegra: Memory Controller Driver (v1) This patch renames the current Memory Controller driver files to "_v1". This is done to add a driver for the new Memory Controller hardware (v2). Change-Id: I668dbba42f6ee0db2f59a7103f0ae7e1d4684ecf Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/common/drivers/memctrl/memctrl.c | 194 -------------------- .../tegra/common/drivers/memctrl/memctrl_v1.c | 195 +++++++++++++++++++++ plat/nvidia/tegra/common/tegra_common.mk | 1 - plat/nvidia/tegra/include/drivers/memctrl.h | 47 ----- plat/nvidia/tegra/include/drivers/memctrl_v1.h | 81 +++++++++ plat/nvidia/tegra/soc/t132/platform_t132.mk | 1 + plat/nvidia/tegra/soc/t210/platform_t210.mk | 1 + 7 files changed, 278 insertions(+), 242 deletions(-) delete mode 100644 plat/nvidia/tegra/common/drivers/memctrl/memctrl.c create mode 100644 plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c create mode 100644 plat/nvidia/tegra/include/drivers/memctrl_v1.h diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c deleted file mode 100644 index 4f7c71e4..00000000 --- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define TEGRA_GPU_RESET_REG_OFFSET 0x28c -#define GPU_RESET_BIT (1 << 24) - -/* Video Memory base and size (live values) */ -static uintptr_t video_mem_base; -static uint64_t video_mem_size; - -/* - * Init SMMU. - */ -void tegra_memctrl_setup(void) -{ - /* - * Setup the Memory controller to allow only secure accesses to - * the TZDRAM carveout - */ - INFO("Configuring SMMU\n"); - - /* allow translations for all MC engines */ - tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, - (unsigned int)MC_SMMU_TRANSLATION_ENABLE); - tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, - (unsigned int)MC_SMMU_TRANSLATION_ENABLE); - tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, - (unsigned int)MC_SMMU_TRANSLATION_ENABLE); - tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, - (unsigned int)MC_SMMU_TRANSLATION_ENABLE); - tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, - (unsigned int)MC_SMMU_TRANSLATION_ENABLE); - - tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); - - tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); - tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); - - /* flush PTC and TLB */ - tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); - (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ - tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); - - /* enable SMMU */ - tegra_mc_write_32(MC_SMMU_CONFIG_0, - MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); - (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ - - /* video memory carveout */ - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); - tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); -} - -/* - * Secure the BL31 DRAM aperture. - * - * phys_base = physical base of TZDRAM aperture - * size_in_bytes = size of aperture in bytes - */ -void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) -{ - /* - * Setup the Memory controller to allow only secure accesses to - * the TZDRAM carveout - */ - INFO("Configuring TrustZone DRAM Memory Carveout\n"); - - tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); - tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); -} - -static void tegra_clear_videomem(uintptr_t non_overlap_area_start, - unsigned long long non_overlap_area_size) -{ - /* - * Perform cache maintenance to ensure that the non-overlapping area is - * zeroed out. The first invalidation of this range ensures that - * possible evictions of dirty cache lines do not interfere with the - * 'zeromem' operation. Other CPUs could speculatively prefetch the - * main memory contents of this area between the first invalidation and - * the 'zeromem' operation. The second invalidation ensures that any - * such cache lines are removed as well. - */ - inv_dcache_range(non_overlap_area_start, non_overlap_area_size); - zeromem((void *)non_overlap_area_start, non_overlap_area_size); - inv_dcache_range(non_overlap_area_start, non_overlap_area_size); -} - -/* - * Program the Video Memory carveout region - * - * phys_base = physical base of aperture - * size_in_bytes = size of aperture in bytes - */ -void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) -{ - uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); - uintptr_t vmem_end_new = phys_base + size_in_bytes; - uint32_t regval; - unsigned long long non_overlap_area_size; - - /* - * The GPU is the user of the Video Memory region. In order to - * transition to the new memory region smoothly, we program the - * new base/size ONLY if the GPU is in reset mode. - */ - regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); - if ((regval & GPU_RESET_BIT) == 0) { - ERROR("GPU not in reset! Video Memory setup failed\n"); - return; - } - - /* - * Setup the Memory controller to restrict CPU accesses to the Video - * Memory region - */ - INFO("Configuring Video Memory Carveout\n"); - - /* - * Configure Memory Controller directly for the first time. - */ - if (video_mem_base == 0) - goto done; - - /* - * Clear the old regions now being exposed. The following cases - * can occur - - * - * 1. clear whole old region (no overlap with new region) - * 2. clear old sub-region below new base - * 3. clear old sub-region above new end - */ - INFO("Cleaning previous Video Memory Carveout\n"); - - disable_mmu_el3(); - if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { - tegra_clear_videomem(video_mem_base, video_mem_size << 20); - } else { - if (video_mem_base < phys_base) { - non_overlap_area_size = phys_base - video_mem_base; - tegra_clear_videomem(video_mem_base, non_overlap_area_size); - } - if (vmem_end_old > vmem_end_new) { - non_overlap_area_size = vmem_end_old - vmem_end_new; - tegra_clear_videomem(vmem_end_new, non_overlap_area_size); - } - } - enable_mmu_el3(0); - -done: - tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); - tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); - - /* store new values */ - video_mem_base = phys_base; - video_mem_size = size_in_bytes >> 20; -} diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c new file mode 100644 index 00000000..ac7d1415 --- /dev/null +++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c @@ -0,0 +1,195 @@ +/* + * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TEGRA_GPU_RESET_REG_OFFSET 0x28c +#define GPU_RESET_BIT (1 << 24) + +/* Video Memory base and size (live values) */ +static uintptr_t video_mem_base; +static uint64_t video_mem_size; + +/* + * Init SMMU. + */ +void tegra_memctrl_setup(void) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Tegra Memory Controller (v1)\n"); + + /* allow translations for all MC engines */ + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_0_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_1_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_2_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_3_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + tegra_mc_write_32(MC_SMMU_TRANSLATION_ENABLE_4_0, + (unsigned int)MC_SMMU_TRANSLATION_ENABLE); + + tegra_mc_write_32(MC_SMMU_ASID_SECURITY_0, MC_SMMU_ASID_SECURITY); + + tegra_mc_write_32(MC_SMMU_TLB_CONFIG_0, MC_SMMU_TLB_CONFIG_0_RESET_VAL); + tegra_mc_write_32(MC_SMMU_PTC_CONFIG_0, MC_SMMU_PTC_CONFIG_0_RESET_VAL); + + /* flush PTC and TLB */ + tegra_mc_write_32(MC_SMMU_PTC_FLUSH_0, MC_SMMU_PTC_FLUSH_ALL); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + tegra_mc_write_32(MC_SMMU_TLB_FLUSH_0, MC_SMMU_TLB_FLUSH_ALL); + + /* enable SMMU */ + tegra_mc_write_32(MC_SMMU_CONFIG_0, + MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE); + (void)tegra_mc_read_32(MC_SMMU_CONFIG_0); /* read to flush writes */ + + /* video memory carveout */ + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, video_mem_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size); +} + +/* + * Secure the BL31 DRAM aperture. + * + * phys_base = physical base of TZDRAM aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + /* + * Setup the Memory controller to allow only secure accesses to + * the TZDRAM carveout + */ + INFO("Configuring TrustZone DRAM Memory Carveout\n"); + + tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base); + tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); +} + +static void tegra_clear_videomem(uintptr_t non_overlap_area_start, + unsigned long long non_overlap_area_size) +{ + /* + * Perform cache maintenance to ensure that the non-overlapping area is + * zeroed out. The first invalidation of this range ensures that + * possible evictions of dirty cache lines do not interfere with the + * 'zeromem' operation. Other CPUs could speculatively prefetch the + * main memory contents of this area between the first invalidation and + * the 'zeromem' operation. The second invalidation ensures that any + * such cache lines are removed as well. + */ + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); + zeromem((void *)non_overlap_area_start, non_overlap_area_size); + inv_dcache_range(non_overlap_area_start, non_overlap_area_size); +} + +/* + * Program the Video Memory carveout region + * + * phys_base = physical base of aperture + * size_in_bytes = size of aperture in bytes + */ +void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) +{ + uintptr_t vmem_end_old = video_mem_base + (video_mem_size << 20); + uintptr_t vmem_end_new = phys_base + size_in_bytes; + uint32_t regval; + unsigned long long non_overlap_area_size; + + /* + * The GPU is the user of the Video Memory region. In order to + * transition to the new memory region smoothly, we program the + * new base/size ONLY if the GPU is in reset mode. + */ + regval = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); + if ((regval & GPU_RESET_BIT) == 0) { + ERROR("GPU not in reset! Video Memory setup failed\n"); + return; + } + + /* + * Setup the Memory controller to restrict CPU accesses to the Video + * Memory region + */ + INFO("Configuring Video Memory Carveout\n"); + + /* + * Configure Memory Controller directly for the first time. + */ + if (video_mem_base == 0) + goto done; + + /* + * Clear the old regions now being exposed. The following cases + * can occur - + * + * 1. clear whole old region (no overlap with new region) + * 2. clear old sub-region below new base + * 3. clear old sub-region above new end + */ + INFO("Cleaning previous Video Memory Carveout\n"); + + disable_mmu_el3(); + if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) { + tegra_clear_videomem(video_mem_base, video_mem_size << 20); + } else { + if (video_mem_base < phys_base) { + non_overlap_area_size = phys_base - video_mem_base; + tegra_clear_videomem(video_mem_base, non_overlap_area_size); + } + if (vmem_end_old > vmem_end_new) { + non_overlap_area_size = vmem_end_old - vmem_end_new; + tegra_clear_videomem(vmem_end_new, non_overlap_area_size); + } + } + enable_mmu_el3(0); + +done: + tegra_mc_write_32(MC_VIDEO_PROTECT_BASE, phys_base); + tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); + + /* store new values */ + video_mem_base = phys_base; + video_mem_size = size_in_bytes >> 20; +} diff --git a/plat/nvidia/tegra/common/tegra_common.mk b/plat/nvidia/tegra/common/tegra_common.mk index 220e2061..82da7fd0 100644 --- a/plat/nvidia/tegra/common/tegra_common.mk +++ b/plat/nvidia/tegra/common/tegra_common.mk @@ -54,7 +54,6 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \ plat/common/aarch64/platform_mp_stack.S \ plat/common/plat_psci_common.c \ ${COMMON_DIR}/aarch64/tegra_helpers.S \ - ${COMMON_DIR}/drivers/memctrl/memctrl.c \ ${COMMON_DIR}/drivers/pmc/pmc.c \ ${COMMON_DIR}/tegra_bl31_setup.c \ ${COMMON_DIR}/tegra_delay_timer.c \ diff --git a/plat/nvidia/tegra/include/drivers/memctrl.h b/plat/nvidia/tegra/include/drivers/memctrl.h index 26c80576..b06b4de7 100644 --- a/plat/nvidia/tegra/include/drivers/memctrl.h +++ b/plat/nvidia/tegra/include/drivers/memctrl.h @@ -31,53 +31,6 @@ #ifndef __MEMCTRL_H__ #define __MEMCTRL_H__ -#include -#include - -/* SMMU registers */ -#define MC_SMMU_CONFIG_0 0x10 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 -#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 -#define MC_SMMU_TLB_CONFIG_0 0x14 -#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 -#define MC_SMMU_PTC_CONFIG_0 0x18 -#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f -#define MC_SMMU_TLB_FLUSH_0 0x30 -#define TLB_FLUSH_VA_MATCH_ALL 0 -#define TLB_FLUSH_ASID_MATCH_DISABLE 0 -#define TLB_FLUSH_ASID_MATCH_SHIFT 31 -#define MC_SMMU_TLB_FLUSH_ALL \ - (TLB_FLUSH_VA_MATCH_ALL | \ - (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) -#define MC_SMMU_PTC_FLUSH_0 0x34 -#define MC_SMMU_PTC_FLUSH_ALL 0 -#define MC_SMMU_ASID_SECURITY_0 0x38 -#define MC_SMMU_ASID_SECURITY 0 -#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 -#define MC_SMMU_TRANSLATION_ENABLE (~0) - -/* TZDRAM carveout configuration registers */ -#define MC_SECURITY_CFG0_0 0x70 -#define MC_SECURITY_CFG1_0 0x74 - -/* Video Memory carveout configuration registers */ -#define MC_VIDEO_PROTECT_BASE 0x648 -#define MC_VIDEO_PROTECT_SIZE_MB 0x64c - -static inline uint32_t tegra_mc_read_32(uint32_t off) -{ - return mmio_read_32(TEGRA_MC_BASE + off); -} - -static inline void tegra_mc_write_32(uint32_t off, uint32_t val) -{ - mmio_write_32(TEGRA_MC_BASE + off, val); -} - void tegra_memctrl_setup(void); void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes); void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes); diff --git a/plat/nvidia/tegra/include/drivers/memctrl_v1.h b/plat/nvidia/tegra/include/drivers/memctrl_v1.h new file mode 100644 index 00000000..e2e05277 --- /dev/null +++ b/plat/nvidia/tegra/include/drivers/memctrl_v1.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of ARM nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MEMCTRLV1_H__ +#define __MEMCTRLV1_H__ + +#include +#include + +/* SMMU registers */ +#define MC_SMMU_CONFIG_0 0x10 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0 +#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1 +#define MC_SMMU_TLB_CONFIG_0 0x14 +#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010 +#define MC_SMMU_PTC_CONFIG_0 0x18 +#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f +#define MC_SMMU_TLB_FLUSH_0 0x30 +#define TLB_FLUSH_VA_MATCH_ALL 0 +#define TLB_FLUSH_ASID_MATCH_DISABLE 0 +#define TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define MC_SMMU_TLB_FLUSH_ALL \ + (TLB_FLUSH_VA_MATCH_ALL | \ + (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) +#define MC_SMMU_PTC_FLUSH_0 0x34 +#define MC_SMMU_PTC_FLUSH_ALL 0 +#define MC_SMMU_ASID_SECURITY_0 0x38 +#define MC_SMMU_ASID_SECURITY 0 +#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98 +#define MC_SMMU_TRANSLATION_ENABLE (~0) + +/* TZDRAM carveout configuration registers */ +#define MC_SECURITY_CFG0_0 0x70 +#define MC_SECURITY_CFG1_0 0x74 + +/* Video Memory carveout configuration registers */ +#define MC_VIDEO_PROTECT_BASE 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c + +static inline uint32_t tegra_mc_read_32(uint32_t off) +{ + return mmio_read_32(TEGRA_MC_BASE + off); +} + +static inline void tegra_mc_write_32(uint32_t off, uint32_t val) +{ + mmio_write_32(TEGRA_MC_BASE + off, val); +} + +#endif /* __MEMCTRLV1_H__ */ diff --git a/plat/nvidia/tegra/soc/t132/platform_t132.mk b/plat/nvidia/tegra/soc/t132/platform_t132.mk index d747d408..466e7cd3 100644 --- a/plat/nvidia/tegra/soc/t132/platform_t132.mk +++ b/plat/nvidia/tegra/soc/t132/platform_t132.mk @@ -48,6 +48,7 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) BL31_SOURCES += lib/cpus/aarch64/denver.S \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_setup.c \ diff --git a/plat/nvidia/tegra/soc/t210/platform_t210.mk b/plat/nvidia/tegra/soc/t210/platform_t210.mk index acc9384d..76bc113d 100644 --- a/plat/nvidia/tegra/soc/t210/platform_t210.mk +++ b/plat/nvidia/tegra/soc/t210/platform_t210.mk @@ -52,6 +52,7 @@ $(eval $(call add_define,MAX_MMAP_REGIONS)) BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ ${COMMON_DIR}/drivers/flowctrl/flowctrl.c \ + ${COMMON_DIR}/drivers/memctrl/memctrl_v1.c \ ${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_sip_calls.c \ ${SOC_DIR}/plat_setup.c \ -- cgit v1.2.3