From 0c8d4fef28768233f1f46b4d085f904293dffd2c Mon Sep 17 00:00:00 2001 From: Achin Gupta Date: Mon, 4 Aug 2014 23:13:10 +0100 Subject: Unmask SError interrupt and clear SCR_EL3.EA bit This patch disables routing of external aborts from lower exception levels to EL3 and ensures that a SError interrupt generated as a result of execution in EL3 is taken locally instead of a lower exception level. The SError interrupt is enabled in the TSP code only when the operation has not been directly initiated by the normal world. This is to prevent the possibility of an asynchronous external abort which originated in normal world from being taken when execution is in S-EL1. Fixes ARM-software/tf-issues#153 Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5 --- bl2/aarch64/bl2_entrypoint.S | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'bl2') diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index d3b0f558..2f058da9 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -53,6 +53,14 @@ func bl2_entrypoint */ adr x0, early_exceptions msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer -- cgit v1.2.3