From cba71b70ef7070bcd38a8d202f30e58f79e36c6b Mon Sep 17 00:00:00 2001 From: Louis Mayencourt Date: Fri, 5 Apr 2019 16:25:25 +0100 Subject: Cortex-A35: Implement workaround for errata 855472 Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt --- docs/cpu-specific-build-macros.rst | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'docs/cpu-specific-build-macros.rst') diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 222c6a7f..0b581692 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -92,6 +92,11 @@ For Cortex-A17, the following errata build flags are defined : - ``ERRATA_A17_852423``: This applies errata 852423 workaround to Cortex-A17 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. +For Cortex-A35, the following errata build flags are defined : + +- ``ERRATA_A35_855472``: This applies errata 855472 workaround to Cortex-A35 + CPUs. This needs to be enabled only for revision r0p0 of Cortex-A35. + For Cortex-A53, the following errata build flags are defined : - ``ERRATA_A53_819472``: This applies errata 819472 workaround to all -- cgit v1.2.3