From 45b52c202f7173d7610e2ca667907a6e646e90fa Mon Sep 17 00:00:00 2001 From: Eleanor Bonnici Date: Wed, 2 Aug 2017 16:35:04 +0100 Subject: Cortex-A57: Implement workaround for erratum 859972 Erratum 855972 applies to revision r1p3 or earlier Cortex-A57 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I56eeac0b753eb1432bd940083372ad6f7e93b16a Signed-off-by: Eleanor Bonnici Signed-off-by: Jeenu Viswambharan --- docs/cpu-specific-build-macros.rst | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'docs/cpu-specific-build-macros.rst') diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 5738927c..6b154f0c 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -30,7 +30,8 @@ errata workaround is ``ERRATA__``, where the ``Processor nam is for example ``A57`` for the ``Cortex_A57`` CPU. Refer to the section *CPU errata status reporting* in -`Firmware Design guide`_ for information on to write errata workaround functions. +`Firmware Design guide`_ for information on how to write errata workaround +functions. All workarounds are disabled by default. The platform is responsible for enabling these workarounds according to its requirement by defining the @@ -98,6 +99,9 @@ For Cortex-A57, following errata build flags are defined : - ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p2 of the CPU. +- ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 + CPU. This needs to be enabled only for revision <= r1p3 of the CPU. + CPU Specific optimizations -------------------------- @@ -131,7 +135,7 @@ architecture that can be enabled by the platform as desired. *Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.* -.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/index.html +.. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf .. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf -- cgit v1.2.3 From 6de9b3364b458160c1229d00667caf93ba93c097 Mon Sep 17 00:00:00 2001 From: Eleanor Bonnici Date: Wed, 2 Aug 2017 18:33:41 +0100 Subject: Cortex-A72: Implement workaround for erratum 859971 Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici Signed-off-by: Jeenu Viswambharan --- docs/cpu-specific-build-macros.rst | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'docs/cpu-specific-build-macros.rst') diff --git a/docs/cpu-specific-build-macros.rst b/docs/cpu-specific-build-macros.rst index 6b154f0c..f74b4593 100644 --- a/docs/cpu-specific-build-macros.rst +++ b/docs/cpu-specific-build-macros.rst @@ -21,6 +21,7 @@ by ARM: - `Cortex-A53 MPCore Software Developers Errata Notice`_ - `Cortex-A57 MPCore Software Developers Errata Notice`_ +- `Cortex-A72 MPCore Software Developers Errata Notice`_ The errata workarounds are implemented for a particular revision or a set of processor revisions. This is checked by the reset handler at runtime. Each @@ -102,6 +103,12 @@ For Cortex-A57, following errata build flags are defined : - ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57 CPU. This needs to be enabled only for revision <= r1p3 of the CPU. + +For Cortex-A72, following errata build flags are defined : + +- ``ERRATA_A72_859971``: This applies errata 859971 workaround to Cortex-A72 + CPU. This needs to be enabled only for revision <= r0p3 of the CPU. + CPU Specific optimizations -------------------------- @@ -137,5 +144,6 @@ architecture that can be enabled by the platform as desired. .. _Cortex-A53 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm048406/Cortex_A53_MPCore_Software_Developers_Errata_Notice.pdf .. _Cortex-A57 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm049219/cortex_a57_mpcore_software_developers_errata_notice.pdf +.. _Cortex-A72 MPCore Software Developers Errata Notice: http://infocenter.arm.com/help/topic/com.arm.doc.epm012079/index.html .. _Firmware Design guide: firmware-design.rst .. _Cortex-A57 Software Optimization Guide: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf -- cgit v1.2.3