From 385f1dbb294b36c5fbdbbf3d10b6cb105239a76e Mon Sep 17 00:00:00 2001 From: Jeenu Viswambharan Date: Tue, 7 Nov 2017 08:38:23 +0000 Subject: GIC: Fix Group 0 enabling At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan --- drivers/arm/gic/v3/gicv3_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/arm/gic/v3/gicv3_private.h') diff --git a/drivers/arm/gic/v3/gicv3_private.h b/drivers/arm/gic/v3/gicv3_private.h index a5093d0c..52039074 100644 --- a/drivers/arm/gic/v3/gicv3_private.h +++ b/drivers/arm/gic/v3/gicv3_private.h @@ -95,7 +95,7 @@ void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base, const unsigned int *sec_intr_list, unsigned int int_grp); #endif -void gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base, +unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base, const interrupt_prop_t *interrupt_props, unsigned int interrupt_props_num); unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base, -- cgit v1.2.3