From b7b0787da84a79733e1ed90a1c15d588c77869e8 Mon Sep 17 00:00:00 2001 From: Soby Mathew Date: Thu, 29 Sep 2016 14:15:57 +0100 Subject: Unify SCTLR initialization for AArch32 normal world The values of CP15BEN, nTWI & nTWE bits in SCTLR_EL1 are architecturally unknown if EL3 is AARCH64 whereas they reset to 1 if EL3 is AArch32. This might be a compatibility break for legacy AArch32 normal world software if these bits are not set to 1 when EL3 is AArch64. This patch enables the CP15BEN, nTWI and nTWE bits in the SCTLR_EL1 if the lower non-secure EL is AArch32. This unifies the SCTLR settings for lower non-secure EL in AArch32 mode for both AArch64 and AArch32 builds of Trusted Firmware. Fixes ARM-software/tf-issues#428 Change-Id: I3152d1580e4869c0ea745c5bd9da765f9c254947 Signed-off-by: Soby Mathew --- include/lib/aarch32/arch.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/lib/aarch32/arch.h') diff --git a/include/lib/aarch32/arch.h b/include/lib/aarch32/arch.h index aba15df1..4968e245 100644 --- a/include/lib/aarch32/arch.h +++ b/include/lib/aarch32/arch.h @@ -108,7 +108,7 @@ /* SCTLR definitions */ #define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ - (1 << 3) | SCTLR_CP15BEN_BIT | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT) + (1 << 3)) #define SCTLR_M_BIT (1 << 0) #define SCTLR_A_BIT (1 << 1) #define SCTLR_C_BIT (1 << 2) @@ -128,7 +128,7 @@ /* HSCTLR definitions */ #define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \ | (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \ - | (1 << 3) | HSCTLR_CP15BEN_BIT) + | (1 << 3)) #define HSCTLR_M_BIT (1 << 0) #define HSCTLR_A_BIT (1 << 1) #define HSCTLR_C_BIT (1 << 2) -- cgit v1.2.3