From f363deb6d409e64de70d25af868a91edb94c186c Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Wed, 3 Jul 2019 13:02:56 +0200 Subject: Rename Cortex-Deimos to Cortex-A77 Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay --- include/lib/cpus/aarch64/cortex_a77.h | 26 ++++++++++++++++++++++++++ include/lib/cpus/aarch64/cortex_deimos.h | 25 ------------------------- 2 files changed, 26 insertions(+), 25 deletions(-) create mode 100644 include/lib/cpus/aarch64/cortex_a77.h delete mode 100644 include/lib/cpus/aarch64/cortex_deimos.h (limited to 'include/lib') diff --git a/include/lib/cpus/aarch64/cortex_a77.h b/include/lib/cpus/aarch64/cortex_a77.h new file mode 100644 index 00000000..0467ef3b --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a77.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A77_H +#define CORTEX_A77_H + +#include + +/* Cortex-A77 MIDR */ +#define CORTEX_A77_MIDR U(0x410FD0D0) + +/******************************************************************************* + * CPU Extended Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Power Control register specific definitions. + ******************************************************************************/ +#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A77_H */ diff --git a/include/lib/cpus/aarch64/cortex_deimos.h b/include/lib/cpus/aarch64/cortex_deimos.h deleted file mode 100644 index 9d024b67..00000000 --- a/include/lib/cpus/aarch64/cortex_deimos.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef CORTEX_DEIMOS_H -#define CORTEX_DEIMOS_H - -#include - -#define CORTEX_DEIMOS_MIDR U(0x410FD0D0) - -/******************************************************************************* - * CPU Extended Control register specific definitions. - ******************************************************************************/ -#define CORTEX_DEIMOS_CPUECTLR_EL1 S3_0_C15_C1_4 - -/******************************************************************************* - * CPU Power Control register specific definitions. - ******************************************************************************/ -#define CORTEX_DEIMOS_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) - -#endif /* CORTEX_DEIMOS_H */ -- cgit v1.2.3