From f363deb6d409e64de70d25af868a91edb94c186c Mon Sep 17 00:00:00 2001 From: Balint Dobszay Date: Wed, 3 Jul 2019 13:02:56 +0200 Subject: Rename Cortex-Deimos to Cortex-A77 Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay --- lib/cpus/aarch64/cortex_a77.S | 71 ++++++++++++++++++++++++++++++++++++++++ lib/cpus/aarch64/cortex_deimos.S | 71 ---------------------------------------- 2 files changed, 71 insertions(+), 71 deletions(-) create mode 100644 lib/cpus/aarch64/cortex_a77.S delete mode 100644 lib/cpus/aarch64/cortex_deimos.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S new file mode 100644 index 00000000..f3fd5e19 --- /dev/null +++ b/lib/cpus/aarch64/cortex_a77.S @@ -0,0 +1,71 @@ +/* + * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex-A77 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex-A77 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* --------------------------------------------- + * HW will do the cache maintenance while powering down + * --------------------------------------------- + */ +func cortex_a77_core_pwr_dwn + /* --------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------- + */ + mrs x0, CORTEX_A77_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A77_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a77_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex-A77. Must follow AAPCS. + */ +func cortex_a77_errata_report + ret +endfunc cortex_a77_errata_report +#endif + + + /* --------------------------------------------- + * This function provides Cortex-A77 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a77_regs, "aS" +cortex_a77_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a77_cpu_reg_dump + adr x6, cortex_a77_regs + mrs x8, CORTEX_A77_CPUECTLR_EL1 + ret +endfunc cortex_a77_cpu_reg_dump + +declare_cpu_ops cortex_a77, CORTEX_A77_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_a77_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_deimos.S b/lib/cpus/aarch64/cortex_deimos.S deleted file mode 100644 index df4c1285..00000000 --- a/lib/cpus/aarch64/cortex_deimos.S +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Deimos must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex-Deimos supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* --------------------------------------------- - * HW will do the cache maintenance while powering down - * --------------------------------------------- - */ -func cortex_deimos_core_pwr_dwn - /* --------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------- - */ - mrs x0, CORTEX_DEIMOS_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_DEIMOS_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_DEIMOS_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_deimos_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Deimos. Must follow AAPCS. - */ -func cortex_deimos_errata_report - ret -endfunc cortex_deimos_errata_report -#endif - - - /* --------------------------------------------- - * This function provides Cortex-Deimos specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_deimos_regs, "aS" -cortex_deimos_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_deimos_cpu_reg_dump - adr x6, cortex_deimos_regs - mrs x8, CORTEX_DEIMOS_CPUECTLR_EL1 - ret -endfunc cortex_deimos_cpu_reg_dump - -declare_cpu_ops cortex_deimos, CORTEX_DEIMOS_MIDR, \ - CPU_NO_RESET_FUNC, \ - cortex_deimos_core_pwr_dwn -- cgit v1.2.3