From 146f4caf3c60fb323db12a4ff3c960c8f08d6f17 Mon Sep 17 00:00:00 2001 From: Bai Ping Date: Thu, 10 May 2018 15:53:11 +0800 Subject: plat: imx8mq: rename files for imx8mq For the i.MX8 media processor, we have i.MX8MQ and i.MX8MM etc. so rename the file name of imx8m_bl31_setup.c and imx8m_psci.c to imx8mq_xxx to make it more clear that these file is specific to i.MX8MQ. Signed-off-by: Bai Ping --- plat/imx/imx8mq/imx8m_bl31_setup.c | 309 ------------------------------------ plat/imx/imx8mq/imx8m_psci.c | 242 ---------------------------- plat/imx/imx8mq/imx8mq_bl31_setup.c | 309 ++++++++++++++++++++++++++++++++++++ plat/imx/imx8mq/imx8mq_psci.c | 242 ++++++++++++++++++++++++++++ plat/imx/imx8mq/platform.mk | 4 +- 5 files changed, 553 insertions(+), 553 deletions(-) delete mode 100644 plat/imx/imx8mq/imx8m_bl31_setup.c delete mode 100644 plat/imx/imx8mq/imx8m_psci.c create mode 100644 plat/imx/imx8mq/imx8mq_bl31_setup.c create mode 100644 plat/imx/imx8mq/imx8mq_psci.c (limited to 'plat') diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c deleted file mode 100644 index 5bea5c0f..00000000 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * Copyright 2017 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* linker defined symbols */ -#if USE_COHERENT_MEM -#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) -#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) -#endif - -#define BL31_RO_BASE (unsigned long)(&__RO_START__) -#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) -#define BL31_END (unsigned long)(&__BL31_END__) - -#define CAAM_BASE (0x30900000) /* HW address*/ - -#define JR0_BASE (CAAM_BASE + 0x1000) - -#define CAAM_JR0MID (0x30900010) -#define CAAM_JR1MID (0x30900018) -#define CAAM_JR2MID (0x30900020) -#define CAAM_NS_MID (0x1) - -#define SM_P0_PERM (JR0_BASE + 0xa04) -#define SM_P0_SMAG2 (JR0_BASE + 0xa08) -#define SM_P0_SMAG1 (JR0_BASE + 0xa0c) -#define SM_CMD (JR0_BASE + 0xbe4) - -/* secure memory command */ -#define SMC_PAGE_SHIFT 16 -#define SMC_PART_SHIFT 8 - -#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ -#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ - -static entry_point_info_t bl32_image_ep_info; -static entry_point_info_t bl33_image_ep_info; - -/* get SPSR for BL33 entry */ -static uint32_t get_spsr_for_bl33_entry(void) -{ - unsigned long el_status; - unsigned long mode; - uint32_t spsr; - - /* figure out what mode we enter the non-secure world */ - el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; - el_status &= ID_AA64PFR0_ELX_MASK; - - mode = (el_status) ? MODE_EL2 : MODE_EL1; - - spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); - return spsr; -} - -#define SCTR_BASE_ADDR 0x306c0000 -#define CNTFID0_OFF 0x20 -#define CNTFID1_OFF 0x24 - -#define SC_CNTCR_ENABLE (1 << 0) -#define SC_CNTCR_HDBG (1 << 1) -#define SC_CNTCR_FREQ0 (1 << 8) -#define SC_CNTCR_FREQ1 (1 << 9) - -#define GPR_TZASC_EN (1 << 0) -#define GPR_TZASC_EN_LOCK (1 << 16) -unsigned int freq; - -void system_counter_init(void) -{ - int val; - - /* Update with accurate clock frequency */ - freq = mmio_read_32(SCTR_BASE_ADDR + CNTFID0_OFF); - - val = mmio_read_32(SCTR_BASE_ADDR + CNTCR_OFF); - val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); - val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; - mmio_write_32(SCTR_BASE_ADDR + CNTCR_OFF, val); -} - -void bl31_tzc380_setup(void) -{ - unsigned int val; - - val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); - if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) - return; - - NOTICE("Configureing TZASC380\n"); - - tzc380_init(IMX_TZASC_BASE); - - /* - * Need to substact offset 0x40000000 from CPU address when - * programming tzasc region for i.mx8mq. - */ - - /* Enable 1G-5G S/NS RW */ - tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); - - tzc380_dump_state(); -} - -void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, - u_register_t arg2, u_register_t arg3) -{ - uint32_t sm_cmd; -#if !defined (CSU_RDC_TEST) - int i; - /* enable CSU NS access permission */ - for (i = 0; i < 64; i++) { - mmio_write_32(0x303e0000 + i * 4, 0xffffffff); - } -#endif - - /* Dealloc part 0 and 2 with current DID */ - sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); - mmio_write_32(SM_CMD, sm_cmd); - - sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); - mmio_write_32(SM_CMD, sm_cmd); - - /* config CAAM JRaMID set MID to Cortex A */ - mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); - mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); - mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); - - /* config the AIPSTZ1 */ - mmio_write_32(0x301f0000, 0x77777777); - mmio_write_32(0x301f0004, 0x77777777); - mmio_write_32(0x301f0040, 0x0); - mmio_write_32(0x301f0044, 0x0); - mmio_write_32(0x301f0048, 0x0); - mmio_write_32(0x301f004c, 0x0); - mmio_write_32(0x301f0050, 0x0); - - /* config the AIPSTZ2 */ - mmio_write_32(0x305f0000, 0x77777777); - mmio_write_32(0x305f0004, 0x77777777); - mmio_write_32(0x305f0040, 0x0); - mmio_write_32(0x305f0044, 0x0); - mmio_write_32(0x305f0048, 0x0); - mmio_write_32(0x305f004c, 0x0); - mmio_write_32(0x305f0050, 0x0); - - /* config the AIPSTZ3 */ - mmio_write_32(0x309f0000, 0x77777777); - mmio_write_32(0x309f0004, 0x77777777); - mmio_write_32(0x309f0040, 0x0); - mmio_write_32(0x309f0044, 0x0); - mmio_write_32(0x309f0048, 0x0); - mmio_write_32(0x309f004c, 0x0); - mmio_write_32(0x309f0050, 0x0); - - /* config the AIPSTZ4 */ - mmio_write_32(0x32df0000, 0x77777777); - mmio_write_32(0x32df0004, 0x77777777); - mmio_write_32(0x32df0040, 0x0); - mmio_write_32(0x32df0044, 0x0); - mmio_write_32(0x32df0048, 0x0); - mmio_write_32(0x32df004c, 0x0); - mmio_write_32(0x32df0050, 0x0); - -#if DEBUG_CONSOLE - console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, - IMX_CONSOLE_BAUDRATE); -#endif - /* enable the system counter */ - system_counter_init(); - - /* Alloc partition 0 writing SMPO and SMAGs */ - mmio_write_32(SM_P0_PERM, 0xff); - mmio_write_32(SM_P0_SMAG2, 0xffffffff); - mmio_write_32(SM_P0_SMAG1, 0xffffffff); - - /* Allocate page 0 and 1 to partition 0 with DID set */ - sm_cmd = (0 << SMC_PAGE_SHIFT - | 0 << SMC_PART_SHIFT - | SMC_CMD_ALLOC_PAGE); - mmio_write_32(SM_CMD, sm_cmd); - - sm_cmd = (1 << SMC_PAGE_SHIFT - | 0 << SMC_PART_SHIFT - | SMC_CMD_ALLOC_PAGE); - mmio_write_32(SM_CMD, sm_cmd); - - /* - * tell BL3-1 where the non-secure software image is located - * and the entry state information. - */ - bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; - bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); - SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); - -#ifdef TEE_IMX8 - /* Populate entry point information for BL32 */ - SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); - SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); - bl32_image_ep_info.pc = BL32_BASE; - bl32_image_ep_info.spsr = 0; - /* Pass TEE base and size to uboot */ - bl33_image_ep_info.args.arg1 = 0xFE000000; - bl33_image_ep_info.args.arg2 = 0x2000000; -#endif - bl31_tzc380_setup(); - -#if defined (CSU_RDC_TEST) - csu_test(); - rdc_test(); -#endif -} - -void bl31_plat_arch_setup(void) -{ - /* add the mmap */ - mmap_add_region(0x900000, 0x900000, 0x20000, - MT_MEMORY | MT_RW); - mmap_add_region(0x100000, 0x100000, 0x10000, - MT_MEMORY | MT_RW); - - mmap_add_region(0x180000, 0x180000, 0x8000, - MT_MEMORY | MT_RW); - - mmap_add_region(0x40000000, 0x40000000, 0xc0000000, - MT_MEMORY | MT_RW | MT_NS); - - mmap_add_region(BL31_BASE, BL31_BASE, BL31_RO_LIMIT - BL31_RO_BASE, - MT_MEMORY | MT_RO); - mmap_add_region(IMX_ROM_BASE, IMX_ROM_BASE, - 0x20000, MT_MEMORY | MT_RO); - /* Map GPV */ - mmap_add_region(0x32000000, 0x32000000, 0x800000, MT_DEVICE | MT_RW); - /* Map AIPS */ - mmap_add_region(IMX_AIPS_BASE, IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW); - - /* Map GIC */ - mmap_add_region(0x38800000, 0x38800000, 0x200000, - MT_DEVICE | MT_RW); - - /* Map DDRC/PHY/PERF */ - mmap_add_region(0x3c000000, 0x3c000000, 0xC000000, MT_DEVICE | MT_RW); - -#if USE_COHERENT_MEM - mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE, - BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE, - MT_DEVICE | MT_RW); -#endif - - /* setup xlat table */ - init_xlat_tables(); - - /* enable the MMU */ - enable_mmu_el3(0); -} - -void bl31_platform_setup(void) -{ - /* init the GICv3 cpu and distributor interface */ - plat_gic_driver_init(); - plat_gic_init(); - - /* gpc init */ - imx_gpc_init(); - - /* switch DDR frequency to 3200 mts */ - lpddr4_switch_to_3200(); -} - -entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) -{ - if (type == NON_SECURE) - return &bl33_image_ep_info; - if (type == SECURE) - return &bl32_image_ep_info; - - return NULL; -} - -unsigned int plat_get_syscnt_freq2(void) -{ - return freq; -} - -void bl31_plat_runtime_setup(void) -{ - return; -} diff --git a/plat/imx/imx8mq/imx8m_psci.c b/plat/imx/imx8mq/imx8m_psci.c deleted file mode 100644 index d0c3b367..00000000 --- a/plat/imx/imx8mq/imx8m_psci.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * Copyright 2017 NXP - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SNVS_LPCR 0x38 - -#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) -#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) -#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) - -const unsigned char imx_power_domain_tree_desc[] = { - /* number of root nodes */ - PWR_DOMAIN_AT_MAX_LVL, - /* number of child at the first node */ - PLATFORM_CLUSTER_COUNT, - PLATFORM_CLUSTER0_CORE_COUNT, -}; - -int imx_pwr_domain_on(u_register_t mpidr) -{ - unsigned int core_id; - uint64_t base_addr = BL31_BASE; - - core_id = MPIDR_AFFLVL0_VAL(mpidr); - - /* set the secure entrypoint */ - imx_set_cpu_secure_entry(core_id, base_addr); - /* power up the core */ - imx_set_cpu_pwr_on(core_id); - - return PSCI_E_SUCCESS; -} - -void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) -{ - /* program the GIC per cpu dist and rdist interface */ - plat_gic_pcpu_init(); - /* enable the GICv3 cpu interface */ - plat_gic_cpuif_enable(); -} - -void imx_pwr_domain_off(const psci_power_state_t *target_state) -{ - uint64_t mpidr = read_mpidr_el1(); - unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); - - /* disable the GIC cpu interface first */ - plat_gic_cpuif_disable(); - /* config the core for power down */ - imx_set_cpu_pwr_off(core_id); -} - -int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) -{ - /* The non-secure entrypoint should be in RAM space */ - if (ns_entrypoint < 0x40000000) - return PSCI_E_INVALID_PARAMS; - - return PSCI_E_SUCCESS; -} - -int imx_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) -{ - int pwr_lvl = psci_get_pstate_pwrlvl(power_state); - int pwr_type = psci_get_pstate_type(power_state); - int state_id = psci_get_pstate_id(power_state); - - if (pwr_lvl > PLAT_MAX_PWR_LVL) - return PSCI_E_INVALID_PARAMS; - - if (pwr_type == PSTATE_TYPE_STANDBY) { - CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; - CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; - } - - if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { - CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; - CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; - } - - return PSCI_E_SUCCESS; -} - -void imx_cpu_standby(plat_local_state_t cpu_state) -{ - dsb(); - write_scr_el3(read_scr_el3() | 0x4); - isb(); - - wfi(); - - write_scr_el3(read_scr_el3() & (~0x4)); - isb(); -} - -void imx_domain_suspend(const psci_power_state_t *target_state) -{ - uint64_t base_addr = BL31_BASE; - uint64_t mpidr = read_mpidr_el1(); - unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); - - if (is_local_state_off(CORE_PWR_STATE(target_state))) { - /* disable the cpu interface */ - plat_gic_cpuif_disable(); - imx_set_cpu_secure_entry(core_id, base_addr); - imx_set_cpu_lpm(core_id, true); - } else { - /* TODO cluster level clock gate off ? */ - dsb(); - write_scr_el3(read_scr_el3() | 0x4); - isb(); - } - - if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) - imx_set_cluster_powerdown(core_id, true); - else - imx_set_cluster_standby(true); - - if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { - /* put DDR into retention mode */ - imx_set_sys_lpm(true); - imx_anamix_pre_suspend(); - } -} - -void imx_domain_suspend_finish(const psci_power_state_t *target_state) -{ - uint64_t mpidr = read_mpidr_el1(); - unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); - - /* check the system level status */ - if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { - imx_set_sys_lpm(false); - imx_anamix_post_resume(); - imx_clear_rbc_count(); - } - - /* check the cluster level power status */ - if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) - imx_set_cluster_powerdown(core_id, false); - else - imx_set_cluster_standby(false); - - /* check the core level power status */ - if (is_local_state_off(CORE_PWR_STATE(target_state))) { - /* clear the core lpm setting */ - imx_set_cpu_lpm(core_id, false); - /* enable the gic cpu interface */ - plat_gic_cpuif_enable(); - } else { - write_scr_el3(read_scr_el3() & (~0x4)); - isb(); - } -} - -void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) -{ - unsigned int i; - - for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) - req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; - - req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; -} - -void __dead2 imx_system_reset(void) -{ - uintptr_t wdog_base = IMX_WDOG_BASE; - unsigned int val; - - /* WDOG_B reset */ - val = mmio_read_16(wdog_base); -#ifdef IMX_WDOG_B_RESET - val = (val & 0x00FF) | (7 << 2) | (1 << 0); -#else - val = (val & 0x00FF) | (4 << 2) | (1 << 0); -#endif - mmio_write_16(wdog_base, val); - - mmio_write_16(wdog_base + 0x2, 0x5555); - mmio_write_16(wdog_base + 0x2, 0xaaaa); - while (1) - ; -} - -void __dead2 imx_system_off(void) -{ - mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, 0x61); - - tf_printf("Unable to poweroff system\n"); - - while (1) - ; -} - -void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) -{ - if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) - imx_set_rbc_count(); - - while (1) - wfi(); -} - -static const plat_psci_ops_t imx_plat_psci_ops = { - .pwr_domain_on = imx_pwr_domain_on, - .pwr_domain_on_finish = imx_pwr_domain_on_finish, - .pwr_domain_off = imx_pwr_domain_off, - .validate_ns_entrypoint = imx_validate_ns_entrypoint, - .validate_power_state = imx_validate_power_state, - .cpu_standby = imx_cpu_standby, - .pwr_domain_suspend = imx_domain_suspend, - .pwr_domain_suspend_finish = imx_domain_suspend_finish, - .pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi, - .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, - .system_reset = imx_system_reset, - .system_off = imx_system_off, -}; - -/* export the platform specific psci ops */ -int plat_setup_psci_ops(uintptr_t sec_entrypoint, - const plat_psci_ops_t **psci_ops) -{ - imx_mailbox_init(sec_entrypoint); - /* sec_entrypoint is used for warm reset */ - *psci_ops = &imx_plat_psci_ops; - - return 0; -} diff --git a/plat/imx/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8mq/imx8mq_bl31_setup.c new file mode 100644 index 00000000..5bea5c0f --- /dev/null +++ b/plat/imx/imx8mq/imx8mq_bl31_setup.c @@ -0,0 +1,309 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* linker defined symbols */ +#if USE_COHERENT_MEM +#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) +#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) +#endif + +#define BL31_RO_BASE (unsigned long)(&__RO_START__) +#define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) + +#define CAAM_BASE (0x30900000) /* HW address*/ + +#define JR0_BASE (CAAM_BASE + 0x1000) + +#define CAAM_JR0MID (0x30900010) +#define CAAM_JR1MID (0x30900018) +#define CAAM_JR2MID (0x30900020) +#define CAAM_NS_MID (0x1) + +#define SM_P0_PERM (JR0_BASE + 0xa04) +#define SM_P0_SMAG2 (JR0_BASE + 0xa08) +#define SM_P0_SMAG1 (JR0_BASE + 0xa0c) +#define SM_CMD (JR0_BASE + 0xbe4) + +/* secure memory command */ +#define SMC_PAGE_SHIFT 16 +#define SMC_PART_SHIFT 8 + +#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */ +#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */ + +static entry_point_info_t bl32_image_ep_info; +static entry_point_info_t bl33_image_ep_info; + +/* get SPSR for BL33 entry */ +static uint32_t get_spsr_for_bl33_entry(void) +{ + unsigned long el_status; + unsigned long mode; + uint32_t spsr; + + /* figure out what mode we enter the non-secure world */ + el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; + el_status &= ID_AA64PFR0_ELX_MASK; + + mode = (el_status) ? MODE_EL2 : MODE_EL1; + + spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); + return spsr; +} + +#define SCTR_BASE_ADDR 0x306c0000 +#define CNTFID0_OFF 0x20 +#define CNTFID1_OFF 0x24 + +#define SC_CNTCR_ENABLE (1 << 0) +#define SC_CNTCR_HDBG (1 << 1) +#define SC_CNTCR_FREQ0 (1 << 8) +#define SC_CNTCR_FREQ1 (1 << 9) + +#define GPR_TZASC_EN (1 << 0) +#define GPR_TZASC_EN_LOCK (1 << 16) +unsigned int freq; + +void system_counter_init(void) +{ + int val; + + /* Update with accurate clock frequency */ + freq = mmio_read_32(SCTR_BASE_ADDR + CNTFID0_OFF); + + val = mmio_read_32(SCTR_BASE_ADDR + CNTCR_OFF); + val &= ~(SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1); + val |= SC_CNTCR_FREQ0 | SC_CNTCR_ENABLE | SC_CNTCR_HDBG; + mmio_write_32(SCTR_BASE_ADDR + CNTCR_OFF, val); +} + +void bl31_tzc380_setup(void) +{ + unsigned int val; + + val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28); + if ((val & GPR_TZASC_EN) != GPR_TZASC_EN) + return; + + NOTICE("Configureing TZASC380\n"); + + tzc380_init(IMX_TZASC_BASE); + + /* + * Need to substact offset 0x40000000 from CPU address when + * programming tzasc region for i.mx8mq. + */ + + /* Enable 1G-5G S/NS RW */ + tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); + + tzc380_dump_state(); +} + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + uint32_t sm_cmd; +#if !defined (CSU_RDC_TEST) + int i; + /* enable CSU NS access permission */ + for (i = 0; i < 64; i++) { + mmio_write_32(0x303e0000 + i * 4, 0xffffffff); + } +#endif + + /* Dealloc part 0 and 2 with current DID */ + sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); + mmio_write_32(SM_CMD, sm_cmd); + + sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART); + mmio_write_32(SM_CMD, sm_cmd); + + /* config CAAM JRaMID set MID to Cortex A */ + mmio_write_32(CAAM_JR0MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR1MID, CAAM_NS_MID); + mmio_write_32(CAAM_JR2MID, CAAM_NS_MID); + + /* config the AIPSTZ1 */ + mmio_write_32(0x301f0000, 0x77777777); + mmio_write_32(0x301f0004, 0x77777777); + mmio_write_32(0x301f0040, 0x0); + mmio_write_32(0x301f0044, 0x0); + mmio_write_32(0x301f0048, 0x0); + mmio_write_32(0x301f004c, 0x0); + mmio_write_32(0x301f0050, 0x0); + + /* config the AIPSTZ2 */ + mmio_write_32(0x305f0000, 0x77777777); + mmio_write_32(0x305f0004, 0x77777777); + mmio_write_32(0x305f0040, 0x0); + mmio_write_32(0x305f0044, 0x0); + mmio_write_32(0x305f0048, 0x0); + mmio_write_32(0x305f004c, 0x0); + mmio_write_32(0x305f0050, 0x0); + + /* config the AIPSTZ3 */ + mmio_write_32(0x309f0000, 0x77777777); + mmio_write_32(0x309f0004, 0x77777777); + mmio_write_32(0x309f0040, 0x0); + mmio_write_32(0x309f0044, 0x0); + mmio_write_32(0x309f0048, 0x0); + mmio_write_32(0x309f004c, 0x0); + mmio_write_32(0x309f0050, 0x0); + + /* config the AIPSTZ4 */ + mmio_write_32(0x32df0000, 0x77777777); + mmio_write_32(0x32df0004, 0x77777777); + mmio_write_32(0x32df0040, 0x0); + mmio_write_32(0x32df0044, 0x0); + mmio_write_32(0x32df0048, 0x0); + mmio_write_32(0x32df004c, 0x0); + mmio_write_32(0x32df0050, 0x0); + +#if DEBUG_CONSOLE + console_init(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, + IMX_CONSOLE_BAUDRATE); +#endif + /* enable the system counter */ + system_counter_init(); + + /* Alloc partition 0 writing SMPO and SMAGs */ + mmio_write_32(SM_P0_PERM, 0xff); + mmio_write_32(SM_P0_SMAG2, 0xffffffff); + mmio_write_32(SM_P0_SMAG1, 0xffffffff); + + /* Allocate page 0 and 1 to partition 0 with DID set */ + sm_cmd = (0 << SMC_PAGE_SHIFT + | 0 << SMC_PART_SHIFT + | SMC_CMD_ALLOC_PAGE); + mmio_write_32(SM_CMD, sm_cmd); + + sm_cmd = (1 << SMC_PAGE_SHIFT + | 0 << SMC_PART_SHIFT + | SMC_CMD_ALLOC_PAGE); + mmio_write_32(SM_CMD, sm_cmd); + + /* + * tell BL3-1 where the non-secure software image is located + * and the entry state information. + */ + bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; + bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); + SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); + +#ifdef TEE_IMX8 + /* Populate entry point information for BL32 */ + SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); + SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); + bl32_image_ep_info.pc = BL32_BASE; + bl32_image_ep_info.spsr = 0; + /* Pass TEE base and size to uboot */ + bl33_image_ep_info.args.arg1 = 0xFE000000; + bl33_image_ep_info.args.arg2 = 0x2000000; +#endif + bl31_tzc380_setup(); + +#if defined (CSU_RDC_TEST) + csu_test(); + rdc_test(); +#endif +} + +void bl31_plat_arch_setup(void) +{ + /* add the mmap */ + mmap_add_region(0x900000, 0x900000, 0x20000, + MT_MEMORY | MT_RW); + mmap_add_region(0x100000, 0x100000, 0x10000, + MT_MEMORY | MT_RW); + + mmap_add_region(0x180000, 0x180000, 0x8000, + MT_MEMORY | MT_RW); + + mmap_add_region(0x40000000, 0x40000000, 0xc0000000, + MT_MEMORY | MT_RW | MT_NS); + + mmap_add_region(BL31_BASE, BL31_BASE, BL31_RO_LIMIT - BL31_RO_BASE, + MT_MEMORY | MT_RO); + mmap_add_region(IMX_ROM_BASE, IMX_ROM_BASE, + 0x20000, MT_MEMORY | MT_RO); + /* Map GPV */ + mmap_add_region(0x32000000, 0x32000000, 0x800000, MT_DEVICE | MT_RW); + /* Map AIPS */ + mmap_add_region(IMX_AIPS_BASE, IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW); + + /* Map GIC */ + mmap_add_region(0x38800000, 0x38800000, 0x200000, + MT_DEVICE | MT_RW); + + /* Map DDRC/PHY/PERF */ + mmap_add_region(0x3c000000, 0x3c000000, 0xC000000, MT_DEVICE | MT_RW); + +#if USE_COHERENT_MEM + mmap_add_region(BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_BASE, + BL31_COHERENT_RAM_LIMIT - BL31_COHERENT_RAM_BASE, + MT_DEVICE | MT_RW); +#endif + + /* setup xlat table */ + init_xlat_tables(); + + /* enable the MMU */ + enable_mmu_el3(0); +} + +void bl31_platform_setup(void) +{ + /* init the GICv3 cpu and distributor interface */ + plat_gic_driver_init(); + plat_gic_init(); + + /* gpc init */ + imx_gpc_init(); + + /* switch DDR frequency to 3200 mts */ + lpddr4_switch_to_3200(); +} + +entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) +{ + if (type == NON_SECURE) + return &bl33_image_ep_info; + if (type == SECURE) + return &bl32_image_ep_info; + + return NULL; +} + +unsigned int plat_get_syscnt_freq2(void) +{ + return freq; +} + +void bl31_plat_runtime_setup(void) +{ + return; +} diff --git a/plat/imx/imx8mq/imx8mq_psci.c b/plat/imx/imx8mq/imx8mq_psci.c new file mode 100644 index 00000000..d0c3b367 --- /dev/null +++ b/plat/imx/imx8mq/imx8mq_psci.c @@ -0,0 +1,242 @@ +/* + * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright 2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SNVS_LPCR 0x38 + +#define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0]) +#define CLUSTER_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL1]) +#define SYSTEM_PWR_STATE(state) ((state)->pwr_domain_state[PLAT_MAX_PWR_LVL]) + +const unsigned char imx_power_domain_tree_desc[] = { + /* number of root nodes */ + PWR_DOMAIN_AT_MAX_LVL, + /* number of child at the first node */ + PLATFORM_CLUSTER_COUNT, + PLATFORM_CLUSTER0_CORE_COUNT, +}; + +int imx_pwr_domain_on(u_register_t mpidr) +{ + unsigned int core_id; + uint64_t base_addr = BL31_BASE; + + core_id = MPIDR_AFFLVL0_VAL(mpidr); + + /* set the secure entrypoint */ + imx_set_cpu_secure_entry(core_id, base_addr); + /* power up the core */ + imx_set_cpu_pwr_on(core_id); + + return PSCI_E_SUCCESS; +} + +void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) +{ + /* program the GIC per cpu dist and rdist interface */ + plat_gic_pcpu_init(); + /* enable the GICv3 cpu interface */ + plat_gic_cpuif_enable(); +} + +void imx_pwr_domain_off(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); + + /* disable the GIC cpu interface first */ + plat_gic_cpuif_disable(); + /* config the core for power down */ + imx_set_cpu_pwr_off(core_id); +} + +int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) +{ + /* The non-secure entrypoint should be in RAM space */ + if (ns_entrypoint < 0x40000000) + return PSCI_E_INVALID_PARAMS; + + return PSCI_E_SUCCESS; +} + +int imx_validate_power_state(unsigned int power_state, + psci_power_state_t *req_state) +{ + int pwr_lvl = psci_get_pstate_pwrlvl(power_state); + int pwr_type = psci_get_pstate_type(power_state); + int state_id = psci_get_pstate_id(power_state); + + if (pwr_lvl > PLAT_MAX_PWR_LVL) + return PSCI_E_INVALID_PARAMS; + + if (pwr_type == PSTATE_TYPE_STANDBY) { + CORE_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + } + + if (pwr_type == PSTATE_TYPE_POWERDOWN && state_id == 0x33) { + CORE_PWR_STATE(req_state) = PLAT_MAX_OFF_STATE; + CLUSTER_PWR_STATE(req_state) = PLAT_MAX_RET_STATE; + } + + return PSCI_E_SUCCESS; +} + +void imx_cpu_standby(plat_local_state_t cpu_state) +{ + dsb(); + write_scr_el3(read_scr_el3() | 0x4); + isb(); + + wfi(); + + write_scr_el3(read_scr_el3() & (~0x4)); + isb(); +} + +void imx_domain_suspend(const psci_power_state_t *target_state) +{ + uint64_t base_addr = BL31_BASE; + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); + + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + /* disable the cpu interface */ + plat_gic_cpuif_disable(); + imx_set_cpu_secure_entry(core_id, base_addr); + imx_set_cpu_lpm(core_id, true); + } else { + /* TODO cluster level clock gate off ? */ + dsb(); + write_scr_el3(read_scr_el3() | 0x4); + isb(); + } + + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) + imx_set_cluster_powerdown(core_id, true); + else + imx_set_cluster_standby(true); + + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + /* put DDR into retention mode */ + imx_set_sys_lpm(true); + imx_anamix_pre_suspend(); + } +} + +void imx_domain_suspend_finish(const psci_power_state_t *target_state) +{ + uint64_t mpidr = read_mpidr_el1(); + unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); + + /* check the system level status */ + if (is_local_state_retn(SYSTEM_PWR_STATE(target_state))) { + imx_set_sys_lpm(false); + imx_anamix_post_resume(); + imx_clear_rbc_count(); + } + + /* check the cluster level power status */ + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) + imx_set_cluster_powerdown(core_id, false); + else + imx_set_cluster_standby(false); + + /* check the core level power status */ + if (is_local_state_off(CORE_PWR_STATE(target_state))) { + /* clear the core lpm setting */ + imx_set_cpu_lpm(core_id, false); + /* enable the gic cpu interface */ + plat_gic_cpuif_enable(); + } else { + write_scr_el3(read_scr_el3() & (~0x4)); + isb(); + } +} + +void imx_get_sys_suspend_power_state(psci_power_state_t *req_state) +{ + unsigned int i; + + for (i = IMX_PWR_LVL0; i < PLAT_MAX_PWR_LVL; i++) + req_state->pwr_domain_state[i] = PLAT_STOP_OFF_STATE; + + req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PLAT_MAX_RET_STATE; +} + +void __dead2 imx_system_reset(void) +{ + uintptr_t wdog_base = IMX_WDOG_BASE; + unsigned int val; + + /* WDOG_B reset */ + val = mmio_read_16(wdog_base); +#ifdef IMX_WDOG_B_RESET + val = (val & 0x00FF) | (7 << 2) | (1 << 0); +#else + val = (val & 0x00FF) | (4 << 2) | (1 << 0); +#endif + mmio_write_16(wdog_base, val); + + mmio_write_16(wdog_base + 0x2, 0x5555); + mmio_write_16(wdog_base + 0x2, 0xaaaa); + while (1) + ; +} + +void __dead2 imx_system_off(void) +{ + mmio_write_32(IMX_SNVS_BASE + SNVS_LPCR, 0x61); + + tf_printf("Unable to poweroff system\n"); + + while (1) + ; +} + +void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) +{ + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) + imx_set_rbc_count(); + + while (1) + wfi(); +} + +static const plat_psci_ops_t imx_plat_psci_ops = { + .pwr_domain_on = imx_pwr_domain_on, + .pwr_domain_on_finish = imx_pwr_domain_on_finish, + .pwr_domain_off = imx_pwr_domain_off, + .validate_ns_entrypoint = imx_validate_ns_entrypoint, + .validate_power_state = imx_validate_power_state, + .cpu_standby = imx_cpu_standby, + .pwr_domain_suspend = imx_domain_suspend, + .pwr_domain_suspend_finish = imx_domain_suspend_finish, + .pwr_domain_pwr_down_wfi = imx_pwr_domain_pwr_down_wfi, + .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, + .system_reset = imx_system_reset, + .system_off = imx_system_off, +}; + +/* export the platform specific psci ops */ +int plat_setup_psci_ops(uintptr_t sec_entrypoint, + const plat_psci_ops_t **psci_ops) +{ + imx_mailbox_init(sec_entrypoint); + /* sec_entrypoint is used for warm reset */ + *psci_ops = &imx_plat_psci_ops; + + return 0; +} diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk index d4ed50e1..936f5348 100644 --- a/plat/imx/imx8mq/platform.mk +++ b/plat/imx/imx8mq/platform.mk @@ -16,11 +16,11 @@ PLAT_DDR_SOURCES := plat/imx/imx8mq/ddr/lpddr4_ddrc_cfg.c \ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/common/mxcuart_console.S \ plat/imx/common/sip_svc.c \ - plat/imx/imx8mq/imx8m_bl31_setup.c \ + plat/imx/imx8mq/imx8mq_bl31_setup.c \ plat/imx/imx8mq/src.c \ plat/imx/imx8mq/hab.c \ plat/imx/imx8mq/gpc.c \ - plat/imx/imx8mq/imx8m_psci.c \ + plat/imx/imx8mq/imx8mq_psci.c \ plat/imx/imx8mq/imx_csu.c \ plat/imx/imx8mq/imx_rdc.c \ plat/imx/common/imx8_topology.c \ -- cgit v1.2.3