boards: tdx-smarc-imx95: enable Cortex-A access to selected gpios

GPIO1 instance is normally configured not to allow access to Cortex-A.
Enable Cortex-A (non secure non privilege) access to these gpio:
- I2C_GP_CK (used for I2C recovery)
- I2C_GP_DAT (used for I2C recovery)
- PMIC_RTC_IRQ_N
- EC_MCU_INT
- CTRL_IO_EXP_INT_B
Allow access to one of the two interrupt sources, as the
current Linux driver (gpio-vf610) only uses the first interrupt.

Related-to: ELB-6257
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>

1 files changed, 29 insertions, 0 deletions

diff --git a/boards/tdx-smarc-imx95/sm/brd_sm.c b/boards/tdx-smarc-imx95/sm/brd_sm.c
index 7715633..5d60d1e 100755
--- a/boards/tdx-smarc-imx95/sm/brd_sm.c
+++ b/boards/tdx-smarc-imx95/sm/brd_sm.c
@@ -114,6 +114,19 @@
 #define BOARD_BOOT_LEVEL  DEV_SM_PERF_LVL_LOW  /* Boot perf low */
 #endif
 
+/* Defines to encode the GPIO1 access protection */
+#define GPIO_PCNS_I2C_GP_CK             RGPIO_PCNS_NSE2_MASK
+#define GPIO_PCNS_I2C_GP_DAT            RGPIO_PCNS_NSE3_MASK
+#define GPIO_PCNS_PMIC_RTC_IRQ_N        RGPIO_PCNS_NSE10_MASK
+#define GPIO_PCNS_EC_MCU_INT            RGPIO_PCNS_NSE11_MASK
+#define GPIO_PCNS_CTRL_IO_EXP_INT_B     RGPIO_PCNS_NSE14_MASK
+
+#define GPIO_PCNP_I2C_GP_CK             RGPIO_PCNP_NSE2_MASK
+#define GPIO_PCNP_I2C_GP_DAT            RGPIO_PCNP_NSE3_MASK
+#define GPIO_PCNP_PMIC_RTC_IRQ_N        RGPIO_PCNP_NPE10_MASK
+#define GPIO_PCNP_EC_MCU_INT            RGPIO_PCNP_NPE11_MASK
+#define GPIO_PCNP_CTRL_IO_EXP_INT_B     RGPIO_PCNP_NPE14_MASK
+
 /* Local types */
 
 /* Local variables */
@@ -167,6 +180,22 @@ int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel)
         BOARD_WdogModeSet(BOARD_WDOG_MODE_FCCU);
     }
 
+    /* Configure non secure non privileged access to
+     * GPIO1 registers and interrupts
+     */
+    GPIO1->PCNS = ( GPIO_PCNS_I2C_GP_CK |
+                    GPIO_PCNS_I2C_GP_DAT |
+                    GPIO_PCNS_PMIC_RTC_IRQ_N |
+                    GPIO_PCNS_EC_MCU_INT |
+                    GPIO_PCNS_CTRL_IO_EXP_INT_B);
+    GPIO1->ICNS = 1;
+    GPIO1->PCNP = ( GPIO_PCNS_I2C_GP_CK |
+                    GPIO_PCNS_I2C_GP_DAT |
+                    GPIO_PCNP_PMIC_RTC_IRQ_N |
+                    GPIO_PCNP_EC_MCU_INT |
+                    GPIO_PCNP_CTRL_IO_EXP_INT_B);
+    GPIO1->ICNP = 1;
+
     /* TODO: Remove when A0 support dropped */
     /* Configure ISO controls based on feature fuses */
     uint32_t ipIsoMask = 0U;