diff options
| author | Ernest Van Hoecke <ernest.vanhoecke@toradex.com> | 2025-09-19 18:30:53 +0200 |
|---|---|---|
| committer | Ernest Van Hoecke <ernest.vanhoecke@toradex.com> | 2025-09-19 18:48:56 +0200 |
| commit | 830080aee78c85c8073f405cecb5edd4b3c6eef1 (patch) | |
| tree | 1aabcf3e20889c56125aaa94ee4851ef62cb1762 | |
| parent | 3e0fc18640a1dab34d93402a97624e0678d5ab49 (diff) | |
board: smarc-imx95: permit access to serial and CAN lines on GPIO1
Grant the non-secure world access to use these lines as GPIOs.
They are not by default used as GPIOs but this allows customers to use
them as such if they want to.
Related-to: ELB-6604
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
| -rwxr-xr-x | boards/tdx-smarc-imx95/sm/brd_sm.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/boards/tdx-smarc-imx95/sm/brd_sm.c b/boards/tdx-smarc-imx95/sm/brd_sm.c index d4b1172..19c5231 100755 --- a/boards/tdx-smarc-imx95/sm/brd_sm.c +++ b/boards/tdx-smarc-imx95/sm/brd_sm.c @@ -116,14 +116,30 @@ /* Defines to encode the GPIO1 access protection */ #define GPIO_PCNS_I2C_GP_CK RGPIO_PCNS_NSE2_MASK #define GPIO_PCNS_I2C_GP_DAT RGPIO_PCNS_NSE3_MASK +#define GPIO_PCNS_SER1_RX RGPIO_PCNS_NSE4_MASK +#define GPIO_PCNS_SER1_TX RGPIO_PCNS_NSE5_MASK +#define GPIO_PCNS_SER0_RX RGPIO_PCNS_NSE6_MASK +#define GPIO_PCNS_SER0_TX RGPIO_PCNS_NSE7_MASK +#define GPIO_PCNS_CAN0_TX RGPIO_PCNS_NSE8_MASK +#define GPIO_PCNS_CAN0_RX RGPIO_PCNS_NSE9_MASK #define GPIO_PCNS_PMIC_RTC_IRQ_N RGPIO_PCNS_NSE10_MASK #define GPIO_PCNS_EC_MCU_INT RGPIO_PCNS_NSE11_MASK +#define GPIO_PCNS_SER0_CTS_B RGPIO_PCNS_NSE12_MASK +#define GPIO_PCNS_SER0_RTS_B RGPIO_PCNS_NSE13_MASK #define GPIO_PCNS_CTRL_IO_EXP_INT_B RGPIO_PCNS_NSE14_MASK #define GPIO_PCNP_I2C_GP_CK RGPIO_PCNP_NSE2_MASK #define GPIO_PCNP_I2C_GP_DAT RGPIO_PCNP_NSE3_MASK +#define GPIO_PCNP_SER1_RX RGPIO_PCNP_NPE4_MASK +#define GPIO_PCNP_SER1_TX RGPIO_PCNP_NPE5_MASK +#define GPIO_PCNP_SER0_RX RGPIO_PCNP_NPE6_MASK +#define GPIO_PCNP_SER0_TX RGPIO_PCNP_NPE7_MASK +#define GPIO_PCNP_CAN0_TX RGPIO_PCNP_NPE8_MASK +#define GPIO_PCNP_CAN0_RX RGPIO_PCNP_NPE9_MASK #define GPIO_PCNP_PMIC_RTC_IRQ_N RGPIO_PCNP_NPE10_MASK #define GPIO_PCNP_EC_MCU_INT RGPIO_PCNP_NPE11_MASK +#define GPIO_PCNP_SER0_CTS_B RGPIO_PCNP_NPE12_MASK +#define GPIO_PCNP_SER0_RTS_B RGPIO_PCNP_NPE13_MASK #define GPIO_PCNP_CTRL_IO_EXP_INT_B RGPIO_PCNP_NPE14_MASK /* Local types */ @@ -184,14 +200,30 @@ int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel) */ GPIO1->PCNS = ( GPIO_PCNS_I2C_GP_CK | GPIO_PCNS_I2C_GP_DAT | + GPIO_PCNS_SER1_RX | + GPIO_PCNS_SER1_TX | + GPIO_PCNS_SER0_RX | + GPIO_PCNS_SER0_TX | + GPIO_PCNS_CAN0_TX | + GPIO_PCNS_CAN0_RX | GPIO_PCNS_PMIC_RTC_IRQ_N | GPIO_PCNS_EC_MCU_INT | + GPIO_PCNS_SER0_CTS_B | + GPIO_PCNS_SER0_RTS_B | GPIO_PCNS_CTRL_IO_EXP_INT_B); GPIO1->ICNS = 1; GPIO1->PCNP = ( GPIO_PCNS_I2C_GP_CK | GPIO_PCNS_I2C_GP_DAT | + GPIO_PCNP_SER1_RX | + GPIO_PCNP_SER1_TX | + GPIO_PCNP_SER0_RX | + GPIO_PCNP_SER0_TX | + GPIO_PCNP_CAN0_TX | + GPIO_PCNP_CAN0_RX | GPIO_PCNP_PMIC_RTC_IRQ_N | GPIO_PCNP_EC_MCU_INT | + GPIO_PCNP_SER0_CTS_B | + GPIO_PCNP_SER0_RTS_B | GPIO_PCNP_CTRL_IO_EXP_INT_B); GPIO1->ICNP = 1; |