board: tdx-smarc-imx95: move GPIO1 access protection to SPLmain

The SPL runs securely. Once U-Boot and later Linux start, we want them
to have control over the GPIOs on GPIO1, so we require non-secure,
non-privileged access at that time.

This is done in the System Manager board code (specifically in
`BRD_SM_Init`), but that runs before the SPL. The GPIO1 registers PCNS
and PCNP act like a switch, so configuring non-secure access before the
SPL runs means that the SPL will not have access. It's either secure or
non-secure access, not both at the same time.

Remove this configuration from the SM, and have the SPL set it up
properly after it is done with the secure access.

Related-to: ELB-6392
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>

1 files changed, 0 insertions, 29 deletions

diff --git a/boards/tdx-smarc-imx95/sm/brd_sm.c b/boards/tdx-smarc-imx95/sm/brd_sm.c
index 5d60d1e..7715633 100755
--- a/boards/tdx-smarc-imx95/sm/brd_sm.c
+++ b/boards/tdx-smarc-imx95/sm/brd_sm.c
@@ -114,19 +114,6 @@
 #define BOARD_BOOT_LEVEL  DEV_SM_PERF_LVL_LOW  /* Boot perf low */
 #endif
 
-/* Defines to encode the GPIO1 access protection */
-#define GPIO_PCNS_I2C_GP_CK             RGPIO_PCNS_NSE2_MASK
-#define GPIO_PCNS_I2C_GP_DAT            RGPIO_PCNS_NSE3_MASK
-#define GPIO_PCNS_PMIC_RTC_IRQ_N        RGPIO_PCNS_NSE10_MASK
-#define GPIO_PCNS_EC_MCU_INT            RGPIO_PCNS_NSE11_MASK
-#define GPIO_PCNS_CTRL_IO_EXP_INT_B     RGPIO_PCNS_NSE14_MASK
-
-#define GPIO_PCNP_I2C_GP_CK             RGPIO_PCNP_NSE2_MASK
-#define GPIO_PCNP_I2C_GP_DAT            RGPIO_PCNP_NSE3_MASK
-#define GPIO_PCNP_PMIC_RTC_IRQ_N        RGPIO_PCNP_NPE10_MASK
-#define GPIO_PCNP_EC_MCU_INT            RGPIO_PCNP_NPE11_MASK
-#define GPIO_PCNP_CTRL_IO_EXP_INT_B     RGPIO_PCNP_NPE14_MASK
-
 /* Local types */
 
 /* Local variables */
@@ -180,22 +167,6 @@ int32_t BRD_SM_Init(int argc, const char * const argv[], uint32_t *mSel)
         BOARD_WdogModeSet(BOARD_WDOG_MODE_FCCU);
     }
 
-    /* Configure non secure non privileged access to
-     * GPIO1 registers and interrupts
-     */
-    GPIO1->PCNS = ( GPIO_PCNS_I2C_GP_CK |
-                    GPIO_PCNS_I2C_GP_DAT |
-                    GPIO_PCNS_PMIC_RTC_IRQ_N |
-                    GPIO_PCNS_EC_MCU_INT |
-                    GPIO_PCNS_CTRL_IO_EXP_INT_B);
-    GPIO1->ICNS = 1;
-    GPIO1->PCNP = ( GPIO_PCNS_I2C_GP_CK |
-                    GPIO_PCNS_I2C_GP_DAT |
-                    GPIO_PCNP_PMIC_RTC_IRQ_N |
-                    GPIO_PCNP_EC_MCU_INT |
-                    GPIO_PCNP_CTRL_IO_EXP_INT_B);
-    GPIO1->ICNP = 1;
-
     /* TODO: Remove when A0 support dropped */
     /* Configure ISO controls based on feature fuses */
     uint32_t ipIsoMask = 0U;