linux-toradex.git, branch ael-12.03.00 Linux kernel for Apalis and Colibri modules ARM: makefile: work around toolchain bug in recent versions of binutils 2012-04-20T13:55:16+00:00 Will Deacon will.deacon@arm.com 2012-04-04T10:28:12+00:00 2a521d1e7167375a8329e94ea110965d36968139 Recent upstream versions of binutils fail to assembler compressed/head.S when passed the -march=all option: http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html The recommended workaround from the tools folks is not to pass the option, and instead let the assembler deduce the CPU type based on the features used by the code. Signed-off-by: Will Deacon <will.deacon@arm.com> 
Recent upstream versions of binutils fail to assembler compressed/head.S
when passed the -march=all option:

http://lists.gnu.org/archive/html/bug-binutils/2011-04/msg00162.html

The recommended workaround from the tools folks is not to pass the
option, and instead let the assembler deduce the CPU type based on the
features used by the code.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: vic: re-read status register before dispatching each IRQ handler 2012-04-20T13:55:15+00:00 Will Deacon will.deacon@arm.com 2012-04-04T09:13:49+00:00 a38d59c28b8fe0ecc00beb4b57b11490105fc1fb handle_IRQ may briefly cause interrupts to be re-enabled during soft IRQ processing on the exit path, leading to nested handling of VIC interrupts. Since the current code does not re-read the VIC_IRQ_STATUS register, this can lead to multiple invocations of the same interrupt handler and spurious interrupts to be reported. This patch changes the VIC interrupt dispatching code to re-read the status register each time, avoiding duplicate invocations of the same handler. Acked-and-tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Will Deacon <will.deacon@arm.com> 
handle_IRQ may briefly cause interrupts to be re-enabled during soft IRQ
processing on the exit path, leading to nested handling of VIC interrupts.

Since the current code does not re-read the VIC_IRQ_STATUS register, this
can lead to multiple invocations of the same interrupt handler and
spurious interrupts to be reported.

This patch changes the VIC interrupt dispatching code to re-read the
status register each time, avoiding duplicate invocations of the same
handler.

Acked-and-tested-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: realview: add defconfig for all realview platforms 2012-04-20T13:55:14+00:00 Will Deacon will.deacon@arm.com 2012-03-29T10:57:23+00:00 cb0ec30dee53229a03f0a41a6010df93450da16b This patch adds a defconfig for ARM realview platforms. Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch adds a defconfig for ARM realview platforms.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: vexpress: add defconfig for all vexpress platforms 2012-04-20T13:55:14+00:00 Will Deacon will.deacon@arm.com 2012-03-28T17:48:26+00:00 03c08e4134933751f152ab9c5cfac0620b3d27eb This patch adds a defconfig for DT-based vexpress platforms. Signed-off-by: Will Deacon <will.deacon@arm.com> 
This patch adds a defconfig for DT-based vexpress platforms.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: l2x0: only write to debug registers on PL310 2012-04-20T13:55:13+00:00 Will Deacon will.deacon@arm.com 2012-03-30T13:26:47+00:00 97b7e43439675b51870b8671cc78f150a04200c3 PL310 errata #588369 and #727915 requires writes to the debug registers of the cache controller to workaround known problems. Writing these registers on L220 may cause deadlock, so ensure that we only perform this operation when we identify a PL310 at probe time. Signed-off-by: Will Deacon <will.deacon@arm.com> 
PL310 errata #588369 and #727915 requires writes to the debug registers
of the cache controller to workaround known problems. Writing these
registers on L220 may cause deadlock, so ensure that we only perform
this operation when we identify a PL310 at probe time.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: l2x0: only apply workaround for erratum #753970 on PL310 2012-04-20T13:55:12+00:00 Will Deacon will.deacon@arm.com 2012-03-30T13:04:49+00:00 9c922678be3594f644190091e4927fdde53d64af The workaround for PL310 erratum #753970 can lead to deadlock on systems with an L220 cache controller. This patch makes the workaround effective only when the cache controller is identified as a PL310 at probe time. Signed-off-by: Will Deacon <will.deacon@arm.com> 
The workaround for PL310 erratum #753970 can lead to deadlock on systems
with an L220 cache controller.

This patch makes the workaround effective only when the cache controller
is identified as a PL310 at probe time.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: hotplug: remove section mismatch on access to pen_release 2012-04-20T13:55:11+00:00 Will Deacon will.deacon@arm.com 2012-03-29T10:52:08+00:00 d086289fdd1735ebeb6d5bb1ae13c7830cf2fcf7 pen_release is marked as __cpuinitdata, so make sure that functions using it are marked with __cpuinit. Signed-off-by: Will Deacon <will.deacon@arm.com> 
pen_release is marked as __cpuinitdata, so make sure that functions
using it are marked with __cpuinit.

Signed-off-by: Will Deacon <will.deacon@arm.com>
ARM: vexpress: plug local timers into the DT code 2012-04-20T13:55:11+00:00 Marc Zyngier marc.zyngier@arm.com 2012-03-28T16:13:53+00:00 dc0b2da7072c76f169defd1064a3f0b51a8ab3bc Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: architected timers: add support for UP timer 2012-04-20T13:55:10+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-20T10:47:00+00:00 7d0946693794c6a5e91b7d597eba50efbd10fdac If CONFIG_LOCAL_TIMERS is not defined, let the architected timer driver register a single clock_event_device that is used as a global timer. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
If CONFIG_LOCAL_TIMERS is not defined, let the architected timer
driver register a single clock_event_device that is used as a
global timer.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
ARM: architected timers: add DT support 2012-04-20T13:55:09+00:00 Marc Zyngier marc.zyngier@arm.com 2012-01-19T13:53:50+00:00 526f1deb0c5fc4e1251a514b7d895928d12d2a41 Add runtime DT support and documentation for the Cortex A7/A15 architected timers. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> 
Add runtime DT support and documentation for the Cortex A7/A15
architected timers.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>