use regulator _sel interface set to support auto delay,
as when regulator's voltage go up, it will take some time
to ramp up to the required voltage, so the delay is necessary.
_sel interface set support such function, now we switch to this
interface set.

Signed-off-by: Anson Huang <b20788@freescale.com>

1.LDO ramp up time may be modified by ROM code
according to fuse setting, cpu freq driver use
fixed delay time which assume the LDO ramp up time
is the reset value of ANATOP register, need to set
it to reset value in regulator init.

2.The regulator set voltage should take care of
the ramp up time, calculate the ramp up time based
of register setting and to the delay, make sure that
when the set voltage function return, the voltage is
stable enough.

3.CPUFreq no need to use delay, it is already taken
care by regulator voltage setting.

Signed-off-by: Anson Huang <b20788@freescale.com>

android framework need seperated hdmi display and hdmi audio switch

Signed-off-by: guoyin.chen <guoyin.chen@freescale.com>

task_free notification procedure cannot be registered/unregistered
during gpu memory allocation dynamically, when the lowmem killer triggers
a kill signal to one app, and then rescan to check if memory is available,
if other 3d apps free some memory prior to the killed app in unlikely case,
then task_free notification procedure will be unregistered before the notification
of the killed app is received, that causes kernel panic in task_free processing.

the fix is to move task_free procedures into gpu kernel drv_init and drv_exit.

Signed-off-by: Xianzhong <b07117@freescale.com>
Acked-by: Lily Zhang

This patch check whether can wake up the device, if not able to
wake up the device, eg, the irq can not request, it will just
not do the suspend & resume.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>

Workaround this issue by not suspend, and this will be check by driver,
if can not request the wake up gpio, it will not do the suspend & resume.

Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>

This patch sets HDMI PHY register values in MXC HDMI driver
platform data so that MXC HDMI driver can configure the
0x09 CKSYMTXCTRL register(Clock Symbol and Transmitter
Control Register) and 0x0E VLEVCTRL register(Voltage Level
Control Register), then we may pass HDMI compliance test
for MX6 HDMI dongle board.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

The PHY register 0x9 and 0xe should setting
to different value in different board to pass HCT.
Add variable phy_reg_vlev and phy_reg_cksymtx to pass
phy config data.

Signed-off-by: Sandor Yu <R01008@freescale.com>
(cherry picked from commit 844aab72e7edcdced9f8e4e0d8e54eb4b0461cd9)

Enabling IPU hsp clock in mxcfb_probe() context by calling
ipu_init_channel() can avoid the IPU display channel(setup
in bootloader) from being damaged by some IPU common driver
APIS which enable/disable IPU hsp clock when doing driver
probe. However, somehow, after LDO bypass patch set is pushed
to kernel, this clock enablement can trigger IPU errors
(IPU_INT_STAT_5 - 0x00800000/IPU_INT_STAT_10 - 0x00100000) and
a display flash. A workaround is to enable IPU hsp clock when
we are at ipu_probe() context, which is earlier than mxcfb_probe()
context, and then to disable(cleanup) the clock once more when
fb_set_par() is triggered by the user for the first time. This
patch updates the comment for ipu_init_channel() and
ipu_enable_channel() in mxcfb_probe() context, and disables ipu
hsp clock when fb_set_par() is triggered by the user for the first
time.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

This patch adds an interface to disable IPU hsp clock so that it
can be called out of ipu common driver.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>