Added non-boot PLL (PLLC/PLLA/PLLD) restoration during clock resume before clock dividers are restored. (Current restoration in RM happens late after clock dividers are restored). Change-Id: I9661f5ddba0ba4b25d5a00c78820792791777429 Reviewed-on: http://git-master/r/5515 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Iqbal Bhinderwala <iqbalb@nvidia.com> Reviewed-by: Rajkumar Jayaraman <rjayaraman@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
The dma can be allocated from multiple client in run time and so it should be thread/smp safe. Returning proper error pointer in case of there is no dma to allocate. bug 723220 Change-Id: Ifb333d4b14e32be561e34a0d7668a2d631ac80c6 (cherry picked from commit db2d10f715fcdd6fdaf5fc7ea8e27a505f8332da) Reviewed-on: http://git-master/r/5769 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
When dma is aborted, all request should be dequeued from the dma and the allocated memory should be freed. The allocated resource was not getting freed, fixing this issue. Properly checking the return pointer from the allocate_dma. (cherry picked from commit 02f0e4da9c66fee14f4492fa5b4ec41fd028a56e) Change-Id: I0dbaeca9b19331458b9aaf91556b7dad1e9b67ee Reviewed-on: http://git-master/r/5768 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
The maximum interface frequency configured by the spi driver should not more than the requested interface freq. Correcting the passed argument to behave the clock driver accordingly. Change-Id: I6e1beea7f01fb410f5e2755406b7d4dac7fd570d Reviewed-on: http://git-master/r/5573 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
The block realignment if a block wasn't split lead to a slow leak of carveout memory if the previous block was not a free block. Change-Id: I08bd89364932f2c4fc4faf1dec177dab03e82a9a Reviewed-on: http://git-master/r/5851 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Thomas Roell <troell@nvidia.com>
merge of the following two patches: ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP The standard I-cache Invalidate All (ICIALLU) and Branch Predication Invalidate All (BPIALL) operations are not automatically broadcast to the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MP This patch fixes the flush_cache_all for ARMv7 SMP.It was missing from commit b8349b569aae661dea9d59d7d2ee587ccea3336c Change-Id: Ie98623b758f8d2d5dabc436ab536ed83efed59f4 Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Cc: <stable@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Reviewed-on: http://git-master/r/5826 Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
On resume restore SDHCI interrupts to the state which was before entering into suspend for SDIO (always_pwr_on) slot. Also, in suspend keep CARD_INT enabled if it was before going to suspend, so that it can be used as wake source. Broadcom wifi driver does not disable/enable SDIO_INT on early_suspend/late_resume, it requires SDIO INTs to be enabled on resume, as even before broadcom driver's late_resume is called which puts wifi is high_pwr, it needs to communicate with MAC for incoming IOCTLs from wpa_supplicant. Bug: 723708 Change-Id: Id1bfe67f415080eeb7563428322dbec3df0f27d2 Reviewed-on: http://git-master/r/5407 Reviewed-by: Rahul Bansal <rbansal@nvidia.com> Tested-by: Rahul Bansal <rbansal@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
1. Changing name field of tegra_vibrator to vibrator 2. Removing vibrator references from board-nvodm.c bug: 702248 Tested on: whistler Change-Id: Ie323e2ee74c4f89b0505f6e3aed1d87f57b388c8 Reviewed-on: http://git-master/r/5795 Tested-by: Venu Byravarasu <vbyravarasu@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
The desired chipselect id which is passed from the slave transaction api is not getting set and so it was not possible to do slave communication on different CS other than 0. Fixing this issue. Change-Id: I91d3b10b7ec01af98a4912ed05f9068491626ba9 Reviewed-on: http://git-master/r/5425 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Tested-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
The external power rail Ext_TPS74201PmuSupply_LDO is controlled by the gpio 1 of the tps6586. When gpio output is set to 0, the rail output is ON and when gpio output is set to 1, the rail output is OFF. As the api provides the control of these external rails through tps6586, the gpio output control should be on the desired value of external rails. Also by default power on, the external power rail Ext_TPS74201PmuSupply_LDO is ON so making it OFF as part of pmu setup. Change-Id: I05e2700afc719065f723b6f78b8cef829dcd4e53 Reviewed-on: http://git-master/r/5558 Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Suresh Mangipudi <smangipudi@nvidia.com> Tested-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>