linux-toradex.git, branch tegra-12r3 Linux kernel for Apalis and Colibri modules ARM: defconfig: enterprise: enable ov9726 sensor 2011-07-01T00:29:16+00:00 Charlie Huang chahuang@nvidia.com 2011-06-29T17:36:05+00:00 c8706adbdcf141cc9f6424a5561ef7e7f309318f bug 829399 - enable front sensor of enterprise board Change-Id: I4d0753d7f82e538cc133dc680924b59a46a9ea82 Reviewed-on: http://git-master/r/39002 Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> Tested-by: Jeremy Wyman <jwyman@nvidia.com> 
bug 829399 - enable front sensor of enterprise board

Change-Id: I4d0753d7f82e538cc133dc680924b59a46a9ea82
Reviewed-on: http://git-master/r/39002
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
Tested-by: Jeremy Wyman <jwyman@nvidia.com>
Revert "i2c: tegra: Remove the synchronization between isr and caller" 2011-07-01T00:19:58+00:00 Zhijun He zhhe@nvidia.com 2011-07-01T00:16:02+00:00 968061f69b9e2e55eb3c291d442a4e90e8334433 This reverts commit fbe412ed91158bc1ec5c30c1bc9e9857a115d754. This fixed the video recording system hang bug. Bug 842901 Change-Id: I9467931ffe57b0d7462f6ca09f7582f9c3c40e46 Reviewed-on: http://git-master/r/39286 Tested-by: Zhijun He <zhhe@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
This reverts commit fbe412ed91158bc1ec5c30c1bc9e9857a115d754.
This fixed the video recording system hang bug.

Bug 842901

Change-Id: I9467931ffe57b0d7462f6ca09f7582f9c3c40e46
Reviewed-on: http://git-master/r/39286
Tested-by: Zhijun He <zhhe@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
ARM: tegra: enterprise: Add front camera 2011-07-01T00:17:32+00:00 Charlie Huang chahuang@nvidia.com 2011-06-29T17:40:07+00:00 8d4a42336fd1bc90f8e4543e82b7494181225eb9 bug 829399 - add front camera ov9726 Change-Id: Iea0db38d3d2a55acf89e9e49a870ecfc4ad0e109 Reviewed-on: http://git-master/r/39003 Reviewed-by: Jihoon Bang <jbang@nvidia.com> Tested-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Chonglei Huang <chahuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
bug 829399 - add front camera ov9726

Change-Id: Iea0db38d3d2a55acf89e9e49a870ecfc4ad0e109
Reviewed-on: http://git-master/r/39003
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Chonglei Huang <chahuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
media: video: tegra: enable ov9726 sensor 2011-07-01T00:17:27+00:00 Charlie Huang chahuang@nvidia.com 2011-06-29T17:44:58+00:00 bcad42d1a0aadaebaaf56fbe4b480cad63fadb3a bug 829399 - add front sensor ov9726 for enterprise board Change-Id: Id775f8d529206c326dbe8c552e049eb49f76fa55 Reviewed-on: http://git-master/r/39005 Reviewed-by: Jihoon Bang <jbang@nvidia.com> Tested-by: Jihoon Bang <jbang@nvidia.com> Reviewed-by: Chonglei Huang <chahuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
bug 829399 - add front sensor ov9726 for enterprise board

Change-Id: Id775f8d529206c326dbe8c552e049eb49f76fa55
Reviewed-on: http://git-master/r/39005
Reviewed-by: Jihoon Bang <jbang@nvidia.com>
Tested-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-by: Chonglei Huang <chahuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
arm: tegra: cardhu: Add KBC wake event 2011-07-01T00:17:12+00:00 Ray Poudrier rapoudrier@nvidia.com 2011-06-30T21:16:42+00:00 cc44260f85612ff49db0738a5b7c46e8e5193fa9 Change-Id: Ifd9d1de52b4859ec16d82287c0944798b6c98d10 Reviewed-on: http://git-master/r/39267 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com> Tested-by: Raymond Poudrier <rapoudrier@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
Change-Id: Ifd9d1de52b4859ec16d82287c0944798b6c98d10
Reviewed-on: http://git-master/r/39267
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
arm: tegra: cardhu: enable lp0 by default 2011-06-30T04:33:03+00:00 Luke Huang lhuang@nvidia.com 2011-06-25T21:34:33+00:00 27765f731c9917332012fdf6dcb80e2c8c205e79 Set the default sleep mode to be lp0. Note: This change only affects Tegra3-A02. For A01, the default sleep mode is still lp1. Bug 802410 Change-Id: Ie9c38333a1048562569333f74bd743960f446ea2 Reviewed-on: http://git-master/r/38780 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
Set the default sleep mode to be lp0.
Note: This change only affects Tegra3-A02. For A01, the default sleep mode is
still lp1.

Bug 802410

Change-Id: Ie9c38333a1048562569333f74bd743960f446ea2
Reviewed-on: http://git-master/r/38780
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
arm: tegra: clock: clock fix for lp0 2011-06-30T04:32:55+00:00 Luke Huang lhuang@nvidia.com 2011-06-25T03:13:09+00:00 52e632bae28a6cf98417ead2dbbdad57854d02d0 Since clock is required when resetting devices, always enable pllc and plla at the beginning of clock restore routine. Change-Id: Ib634408f23677ce1cf629576130bbc5a6ca767af Reviewed-on: http://git-master/r/38778 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
Since clock is required when resetting devices, always enable pllc and plla at
the beginning of clock restore routine.

Change-Id: Ib634408f23677ce1cf629576130bbc5a6ca767af
Reviewed-on: http://git-master/r/38778
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
arm: tegra: cardhu: disable governor switching on early suspend 2011-06-30T04:32:48+00:00 Luke Huang lhuang@nvidia.com 2011-06-29T02:10:22+00:00 7805e0584bcd937cf8a550b9db305435ea68bce8 governor swithing is causing the system to fail on LP0 resume. Disable it for now. DO NOT merge back to main. Change-Id: Id2ffcbd9657b8abff7c943e1d62e16b4a14e0b42 Reviewed-on: http://git-master/r/38853 Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Tested-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Wen Yi <wyi@nvidia.com> Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
governor swithing is causing the system to fail on LP0 resume. Disable it for
now.

DO NOT merge back to main.

Change-Id: Id2ffcbd9657b8abff7c943e1d62e16b4a14e0b42
Reviewed-on: http://git-master/r/38853
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
ARM: tegra: power: Powergate PCIE and SATA partitions on tegra 3 2011-06-30T04:31:06+00:00 Karan Jhavar kjhavar@nvidia.com 2011-06-09T21:50:35+00:00 319f18e426b22e2bcb86a2e0d46f2851d642fea5 By defalut PCIE and SATA partitions are powergated. If needed, respective drivers should un-powergate these partitions. Change-Id: Ibe2ada3e8b9738393140ad3dbbd7af4a9d94e889 Reviewed-on: http://git-master/r/38816 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
By defalut PCIE and SATA partitions are powergated. If needed,
respective drivers should un-powergate these partitions.

Change-Id: Ibe2ada3e8b9738393140ad3dbbd7af4a9d94e889
Reviewed-on: http://git-master/r/38816
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>
cpufreq interactive governor: Update target frequency calculation 2011-06-30T04:30:49+00:00 Alex Frid afrid@nvidia.com 2011-05-28T03:53:27+00:00 c9c615cc728d77d9ab123bfeeba868bea7e26c9f Updated target frequency calculation algorithm to take into account current rate CPU is running at: - When CPU is running below go_maxspeed_load threshold, adjust the target frequency based on current rate to reach tunable sustainable load (instead of applying cpu load to max possible cpu rate). Tuned by setting new node ("0" falls back to using max_rate): /sys/devices/system/cpu/cpufreq/interactive/sustain_load - When CPU is running at/above go_maxspeed_load threshold, ramp the target frequency starting from current exponentially with tunable base (instead of immediate jump to maximum cpu rate). Tuned by setting new node ("0" falls back to jump to max_rate): /sys/devices/system/cpu/cpufreq/interactive/boost_factor Defaults for the new tunning parameters are set to "0" - so no changes in governor default behavior. Change-Id: I0137c2fbc9c2cc1ae85869593319324d31974e1a Reviewed-on: http://git-master/r/38817 Reviewed-by: Karan Jhavar <kjhavar@nvidia.com> Tested-by: Karan Jhavar <kjhavar@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com> Reviewed-by: Jeremy Wyman <jwyman@nvidia.com> 
Updated target frequency calculation algorithm to take into account
current rate CPU is running at:

- When CPU is running below go_maxspeed_load threshold, adjust the
target frequency based on current rate to reach tunable sustainable
load (instead of applying cpu load to max possible cpu rate).

Tuned by setting new node ("0" falls back to using max_rate):
/sys/devices/system/cpu/cpufreq/interactive/sustain_load

- When CPU is running at/above go_maxspeed_load threshold, ramp the
target frequency starting from current exponentially with tunable base
(instead of immediate jump to maximum cpu rate).

Tuned by setting new node ("0" falls back to jump to max_rate):
/sys/devices/system/cpu/cpufreq/interactive/boost_factor

Defaults for the new tunning parameters are set to "0" - so no changes
in governor default behavior.

Change-Id: I0137c2fbc9c2cc1ae85869593319324d31974e1a
Reviewed-on: http://git-master/r/38817
Reviewed-by: Karan Jhavar <kjhavar@nvidia.com>
Tested-by: Karan Jhavar <kjhavar@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Jeremy Wyman <jwyman@nvidia.com>