linux-toradex.git, branch tegra-9.12.7 Linux kernel for Apalis and Colibri modules Tegra RM: Removed 50MHz floor for MIPI PLL output. 2010-03-08T23:49:46+00:00 Alex Frid afrid@nvidia.com 2010-03-06T03:08:02+00:00 ab7b7f907c9b7ae9812581ff5535fd98474ba76b Removed 50MHz floor for MIPI PLL high speed output frequency. This floor kept MIPI PLL low speed output (= high speed output / 8) above DSI panel specification - bug 651446. Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a Reviewed-on: http://git-master/r/787 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com> Tested-by: Venkata (Muni) Anda <vanda@nvidia.com> 
Removed 50MHz floor for MIPI PLL high speed output frequency. This
floor kept MIPI PLL low speed output (= high speed output / 8) above
DSI panel specification - bug 651446.

Change-Id: Id1d3314b46896cc8f6fb48d238ffed01fd6b4e4a
Reviewed-on: http://git-master/r/787
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Venkata (Muni) Anda <vanda@nvidia.com>
Tested-by: Venkata (Muni) Anda <vanda@nvidia.com>
[nvmap] fix strided read/write loop increment 2010-03-08T22:13:22+00:00 Gary King gking@nvidia.com 2010-03-08T22:08:59+00:00 4646176e2e325e692423dfbee0f07f88210f36f1 in the process of cleaning up the implementation of do_rw so that it could be called from both ioctl and kernel contexts, the loop increment for source and distination addresses was erroneously set to the element size, rather than the provided strides. bug 660448 Change-Id: I02e2b2b980f90a2171d811192b667883f2a3ab41 Reviewed-on: http://git-master/r/805 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
in the process of cleaning up the implementation of do_rw so
that it could be called from both ioctl and kernel contexts,
the loop increment for source and distination addresses
was erroneously set to the element size, rather than the
provided strides.

bug 660448

Change-Id: I02e2b2b980f90a2171d811192b667883f2a3ab41
Reviewed-on: http://git-master/r/805
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
tegra uart: Make device id equal to instance id 2010-03-08T18:06:29+00:00 Rama Kandhala rkandhala@nvidia.com 2010-03-05T06:24:41+00:00 0c2c9956982663d23373ac7ac7c3bfea57f5d2ae Changed the registration to use the device ID same as instance. With this change instance 0 will show up as ttyHS0 and instance 1 will show up as ttyHS1 and so on. Before this change, if the instance 0 was not used on a platform, instance 1 would have showed up as ttyHS0. Bug 656451 Tested with Harmony. Made sure that all nodes showup in the device list except the missing instance. Change-Id: Ib4e04b12f16002deb899b38630de102c24e588b0 Reviewed-on: http://git-master/r/735 Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
Changed the registration to use the device ID same as instance.
With this change instance 0 will show up as ttyHS0 and instance 1
will show up as ttyHS1 and so on. Before this change, if the instance 0
was not used on a platform, instance 1 would have showed up as ttyHS0.

Bug 656451
Tested with Harmony.
Made sure that all nodes showup in the device list except the missing instance.
Change-Id: Ib4e04b12f16002deb899b38630de102c24e588b0
Reviewed-on: http://git-master/r/735
Reviewed-by: Ramachandrudu Kandhala <rkandhala@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
tegra: Commenting the error prints for memory pin/Unpin functions 2010-03-08T17:59:55+00:00 Ninad Malwade nmalwade@nvidia.com 2010-03-08T06:18:25+00:00 3cb112b319306cd993cb421577035c03be05723a - On behalf of Gautam Moharir - Bug 660462 Change-Id: I66e22e247ce5df6135f31c75ae91ec5d0b11e666 Reviewed-on: http://git-master/r/792 Reviewed-by: Ninad Malwade <nmalwade@nvidia.com> Tested-by: Ninad Malwade <nmalwade@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
- On behalf of Gautam Moharir
- Bug 660462

Change-Id: I66e22e247ce5df6135f31c75ae91ec5d0b11e666
Reviewed-on: http://git-master/r/792
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
[arm] implement TLS register workaround for Tegra errata 657451 2010-03-06T05:21:51+00:00 Gary King gking@nvidia.com 2010-03-05T05:27:18+00:00 227af643e6253e9a5c2a2f74468f855686c44117 tegra 2 systems have a hardware errata which causes bit 20 of the TLS register (CP15 c13, operations 2-4) to be unreliable. in common user space threading libraries (glibc pthreads, bionic pthreads), the value stored in this register is guaranteed to be at least word-aligned, leaving bit 0 free. the work-around for this hardware errata is storing bit 20 of the user space-provided TLS value into bit 0 of the register inside __set_tls, and restoring it in the get_tls helper. Change-Id: I06439378edc01dc897708e3298cd91b5721c6e50 Reviewed-on: http://git-master/r/779 Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Arthur Spence <aspence@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
tegra 2 systems have a hardware errata which causes bit 20 of the
TLS register (CP15 c13, operations 2-4) to be unreliable.

in common user space threading libraries (glibc pthreads, bionic
pthreads), the value stored in this register is guaranteed to be
at least word-aligned, leaving bit 0 free.

the work-around for this hardware errata is storing bit 20 of the
user space-provided TLS value into bit 0 of the register inside
__set_tls, and restoring it in the get_tls helper.

Change-Id: I06439378edc01dc897708e3298cd91b5721c6e50
Reviewed-on: http://git-master/r/779
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Arthur Spence <aspence@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
[tegra iovmm] implement stubs for no-iovmm case 2010-03-06T01:31:44+00:00 Gary King gking@nvidia.com 2010-03-06T01:17:56+00:00 da64ef9eab8bf0fc07cd8abbbdf494b67c9971f1 nvmap build fails when CONFIG_TEGRA_IOVMM is not selected. add stubs to allow that combination to work. Change-Id: Ie7e47a987feaeffd987996d11a594b2c8551311e Reviewed-on: http://git-master/r/785 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
nvmap build fails when CONFIG_TEGRA_IOVMM is not selected. add stubs
to allow that combination to work.

Change-Id: Ie7e47a987feaeffd987996d11a594b2c8551311e
Reviewed-on: http://git-master/r/785
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
Tegra pm:disable pllp pll during system suspend. other code cleanup 2010-03-05T22:38:03+00:00 Narendra Damahe ndamahe@nvidia.com 2010-03-05T01:54:17+00:00 3a5eff5302d66bd471c4a4778505f5211776ecd3 Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d Reviewed-on: http://git-master/r/750 Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Narendra Damahe <ndamahe@nvidia.com> Tested-by: Narendra Damahe <ndamahe@nvidia.com> Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com> 
Change-Id: 	I02aa2fd9d5a4faa830e838d2705ee81058fe001d
Change-Id: I02aa2fd9d5a4faa830e838d2705ee81058fe001d
Reviewed-on: http://git-master/r/750
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Tested-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
tegra-nvodm-touch: Remove unneed condition check width[0] == 0xf 2010-03-05T22:11:29+00:00 Hoang Pham hopham@nvidia.com 2010-03-04T18:52:26+00:00 c96a771e6915bbb845c57dab78d78b3c352ae070 This condition check width[0] == 0xf is not need based on spec and it is causing second finger samples are ignored many times. Fixes bug 653317 Change-Id: I2ada2732f0c4965817a0ed1dca1b6351e01d256a Reviewed-on: http://git-master/r/769 Reviewed-by: Gary King <gking@nvidia.com> Reviewed-by: Varun Wadekar <vwadekar@nvidia.com> Tested-by: Varun Wadekar <vwadekar@nvidia.com> 
This condition check width[0] == 0xf is not need based on spec
and it is causing second finger samples are ignored many times.

Fixes bug 653317

Change-Id: I2ada2732f0c4965817a0ed1dca1b6351e01d256a
Reviewed-on: http://git-master/r/769
Reviewed-by: Gary King <gking@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
tegra: EHCI bus suspend/resume requires CONFIG_PM 2010-03-05T21:55:32+00:00 Scott Williams scwilliams@nvidia.com 2010-03-05T18:46:36+00:00 bc646f81bff16fbb813977d9b926b04a32acf8ce If CONFIG_PM is not selected, don't compile EHCI bus suspend/resume. Change-Id: Ia89612fa3d82dc671accc597e4d1ca05f56eaa5c Reviewed-on: http://git-master/r/783 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
If CONFIG_PM is not selected, don't compile EHCI bus suspend/resume.

Change-Id: Ia89612fa3d82dc671accc597e4d1ca05f56eaa5c
Reviewed-on: http://git-master/r/783
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>
[nvmap] handle NULL return for pin multiple, fix infinite loop 2010-03-05T19:04:19+00:00 Gary King gking@nvidia.com 2010-03-05T18:41:32+00:00 e017a62d01aa6c7d0253b15182669295f000fa03 the handle alignment parameter query had an off-by-one bug in its loop initializer which caused any carveout handle to trigger an infinite loop. the only caller of this API was the debug EGL driver, which used it to verify that the allocation matched the requested alignment. also, if the user passes NULL as the address array when pinning multiple handles to ioctl_pinop, pin the handles and skip the output write, rather than returning a permission error. big thanks to antti for finding the infinite loop. bug 660526 Change-Id: I90f819a231b5a8bef5b473252122cdbefc744efb Reviewed-on: http://git-master/r/782 Reviewed-by: Gary King <gking@nvidia.com> Tested-by: Gary King <gking@nvidia.com> 
the handle alignment parameter query had an off-by-one bug in its
loop initializer which caused any carveout handle to trigger an
infinite loop. the only caller of this API was the debug EGL
driver, which used it to verify that the allocation matched
the requested alignment.

also, if the user passes NULL as the address array when pinning
multiple handles to ioctl_pinop, pin the handles and skip the
output write, rather than returning a permission error.

big thanks to antti for finding the infinite loop.

bug 660526
Change-Id: I90f819a231b5a8bef5b473252122cdbefc744efb
Reviewed-on: http://git-master/r/782
Reviewed-by: Gary King <gking@nvidia.com>
Tested-by: Gary King <gking@nvidia.com>