linux-toradex.git, branch tegra-l4t-r21.5 Linux kernel for Apalis and Colibri modules ata: ahci_tegra: disable DIPM 2016-05-28T00:57:24+00:00 Preetham Chandru R pchandru@nvidia.com 2016-02-23T06:24:34+00:00 a7da876159f2b71ad411c31d08030be2e99dd417 DIPM is not a POR for Tegra AHCI Sata Controller Bug 200087528 Change-Id: I5a742170177c9f57426f3756a8cfafefa88af92b Signed-off-by: Preetham Chandru R <pchandru@nvidia.com> Reviewed-on: http://git-master/r/1013776 (cherry picked from commit 7ebd3b1058491ee87686e9e731b79ecd914e00d9) Reviewed-on: http://git-master/r/1031624 Reviewed-by: Bibek Basu <bbasu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com> 
DIPM is not a POR for Tegra AHCI Sata Controller

Bug 200087528

Change-Id: I5a742170177c9f57426f3756a8cfafefa88af92b
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>
Reviewed-on: http://git-master/r/1013776
(cherry picked from commit 7ebd3b1058491ee87686e9e731b79ecd914e00d9)
Reviewed-on: http://git-master/r/1031624
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
platform: tegra: nvavp: fix for pre-decrement of clk_enabled cntr 2016-05-27T05:57:35+00:00 Bhushan Rupde brupde@nvidia.com 2016-05-13T09:00:19+00:00 8b409a3da4069a6c3831e7fa1f847fd86d800353 Bug 1729847 Change-Id: Ie455b0469a1d4e35453ca9e36c5e90dfdc6f56a2 Signed-off-by: Bhushan Rupde <brupde@nvidia.com> Reviewed-on: http://git-master/r/1147432 Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com> Reviewed-by: Soumen Dey <sdey@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> 
Bug 1729847

Change-Id: Ie455b0469a1d4e35453ca9e36c5e90dfdc6f56a2
Signed-off-by: Bhushan Rupde <brupde@nvidia.com>
Reviewed-on: http://git-master/r/1147432
Reviewed-by: Mohan Nimaje <mnimaje@nvidia.com>
Reviewed-by: Soumen Dey <sdey@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
video: tegra: host: Fix ch open error handling 2016-05-24T23:04:24+00:00 Arto Merilainen amerilainen@nvidia.com 2016-05-10T06:16:03+00:00 58e3084c00ca7b7ae59f906bb4e1948b0f1e291f In case kernel fails to open a channel (e.g. due to inability to allocate hardware context or turn on the device), the channel open function releases the resources that were already allocated successfully. However, currently the error path additionally calls the channel release function for putting the channel pointer after the private data structures have been freed - thereby causing use-after-free memory usage. This patch reworks error handling in channel open to release channel without risking usage of already freed memory. Bug 1763577 Change-Id: Ic7562e69f2babad653afc7a11e413701494a30b4 Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-on: http://git-master/r/1148081 Reviewed-by: Winnie Hsu <whsu@nvidia.com> Tested-by: Winnie Hsu <whsu@nvidia.com> 
In case kernel fails to open a channel (e.g. due to inability to
allocate hardware context or turn on the device), the channel open
function releases the resources that were already allocated
successfully.

However, currently the error path additionally calls the channel
release function for putting the channel pointer after the private
data structures have been freed - thereby causing use-after-free
memory usage.

This patch reworks error handling in channel open to release
channel without risking usage of already freed memory.

Bug 1763577

Change-Id: Ic7562e69f2babad653afc7a11e413701494a30b4
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-on: http://git-master/r/1148081
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Tested-by: Winnie Hsu <whsu@nvidia.com>
video: tegra: host: check if offset is u32 aligned 2016-05-23T17:24:19+00:00 Deepak Nibade dnibade@nvidia.com 2016-03-11T08:29:20+00:00 bb7faf0544ccc7c310c27dd43857dc2a62fc7e5c In nvhost_ioctl_ctrl_module_regrdwr(), we copy offset to read/write from user space but we do not have any check on it So it is possible for user space to add unaligned offset and request read/write which would crash the system Fix this by explicitly checking alignment of the offset passed by user space Bug 1739935 Change-Id: Iea2a07c60500af876b732a0e9d9d08535aa53b5c Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1029405 (cherry picked from commit 422baa09a17a6a17f4e572aa5441ca174634de0d) Reviewed-on: http://git-master/r/1123363 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Tested-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com> 
In nvhost_ioctl_ctrl_module_regrdwr(), we copy offset
to read/write from user space but we do not have
any check on it

So it is possible for user space to add unaligned
offset and request read/write which would crash the
system

Fix this by explicitly checking alignment of the
offset passed by user space

Bug 1739935

Change-Id: Iea2a07c60500af876b732a0e9d9d08535aa53b5c
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1029405
(cherry picked from commit 422baa09a17a6a17f4e572aa5441ca174634de0d)
Reviewed-on: http://git-master/r/1123363
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Tested-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
camera: tegra: Fix security vulnerability issue 2016-05-23T17:24:10+00:00 Frank Chen frankc@nvidia.com 2016-03-25T05:37:18+00:00 04ac7e0011f9845b69c4be3bedf058a350ca814c Deprecate outdated UPDATE_GPIO function in camera.pcl driver. This function is not used by any code anymore and is a security vulnerability since it is trying to access user mode pointer directly. Bug 1745102 Change-Id: I4e7e5f9c186f980dcadfe52ec4284102255f19cf Signed-off-by: Frank Chen <frankc@nvidia.com> Reviewed-on: http://git-master/r/1115302 (cherry picked from commit 2e5c355c904a19d71456a04c70f3fb4fc7d918b0) Reviewed-on: http://git-master/r/1123362 Reviewed-by: Matthew Pedro <mapedro@nvidia.com> Tested-by: Matthew Pedro <mapedro@nvidia.com> 
Deprecate outdated UPDATE_GPIO function in camera.pcl
driver. This function is not used by any code anymore
and is a security vulnerability since it is trying to
access user mode pointer directly.

Bug 1745102

Change-Id: I4e7e5f9c186f980dcadfe52ec4284102255f19cf
Signed-off-by: Frank Chen <frankc@nvidia.com>
Reviewed-on: http://git-master/r/1115302
(cherry picked from commit 2e5c355c904a19d71456a04c70f3fb4fc7d918b0)
Reviewed-on: http://git-master/r/1123362
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
Tested-by: Matthew Pedro <mapedro@nvidia.com>
camera: tegra: Fix security vulnerability issue 2016-05-20T17:59:11+00:00 Frank Chen frankc@nvidia.com 2016-03-21T17:40:45+00:00 1275778d6d510a62c884afc7494bd7cd055855ee We need to validate power on/off function size passed in from user mode in order to avoid integer overflow or out of memory failures. Bug 1745100 Change-Id: Idddd848f7dc1e864559ad219f9204325128484e5 Signed-off-by: Frank Chen <frankc@nvidia.com> Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1114354 (cherry picked from commit 8b3afcc132882f3102083f9a24de7f55476ca59b) Reviewed-on: http://git-master/r/1150944 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com> 
We need to validate power on/off function size passed
in from user mode in order to avoid integer overflow
or out of memory failures.

Bug 1745100

Change-Id: Idddd848f7dc1e864559ad219f9204325128484e5
Signed-off-by: Frank Chen <frankc@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/1114354
(cherry picked from commit 8b3afcc132882f3102083f9a24de7f55476ca59b)
Reviewed-on: http://git-master/r/1150944
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
media: tegra: camera: Fix stack overread 2016-05-20T17:59:01+00:00 Amey Asgaonkar aasgaonkar@nvidia.com 2016-05-16T23:33:15+00:00 14359cb871606ffefa4ca2070b7e9ccb08dcd378 We are not checking a variable which is user controlled. This can lead to reading of the stack data. Adding a check to ensure it is less than the max possible value of the variable. Bug 1763649 Change-Id: I395e882d030199bdd7684837906a9b5d60741650 Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com> Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1150943 GVS: Gerrit_Virtual_Submit Reviewed-by: Matthew Pedro <mapedro@nvidia.com> 
We are not checking a variable which is user
controlled. This can lead to reading of the
stack data. Adding a check to ensure it is
less than the max possible value of the variable.

Bug 1763649

Change-Id: I395e882d030199bdd7684837906a9b5d60741650
Signed-off-by: Amey Asgaonkar <aasgaonkar@nvidia.com>
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/1150943
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>
arm: tegra: new dvfs update for aging factor 2016-05-16T22:47:59+00:00 Bibek Basu bbasu@nvidia.com 2016-05-06T10:08:26+00:00 029cec3ad88a18829e816ad56ed5c7da06955199 Following support added DVFS for Gauranteed freq considering aging CPU freq limit at higher temperature EDP max current limits for each SKU Bug 200195229 Change-Id: If00f3fd6b891cf366047dda331bd7ab1c15b40f7 Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1146577 GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com> 
Following support added
DVFS for Gauranteed freq considering aging
CPU freq limit at higher temperature
EDP max current limits for each SKU

Bug 200195229

Change-Id: If00f3fd6b891cf366047dda331bd7ab1c15b40f7
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/1146577
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: tegra: emc dvfs selection based on ddr 2016-05-13T21:53:15+00:00 Bibek Basu bbasu@nvidia.com 2016-05-10T10:31:17+00:00 41cb0eedb8af2a408c1d2c47ebf345a6db99912e select emc evfs table based on DDR present using RAMCODE Bug 200195279 Change-Id: I7fbc693383c9e231b2c2119020eebc7bba544c6e Signed-off-by: Bibek Basu <bbasu@nvidia.com> Reviewed-on: http://git-master/r/1144528 Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Winnie Hsu <whsu@nvidia.com> 
select emc evfs table based on DDR present
using RAMCODE

Bug 200195279

Change-Id: I7fbc693383c9e231b2c2119020eebc7bba544c6e
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/1144528
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
arm: config: T124: L4T: systemd related configs 2016-05-02T17:50:37+00:00 Ninad Malwade nmalwade@nvidia.com 2016-04-29T06:55:48+00:00 8e840813f3dabcf4ace93e6bb6eb590b813c1f14 Added kernel configurations to support systemd functionality boot.img size is increased by 69632 bytes Bug 1731796 Change-Id: I4209fee15843ac645600500ed8c9fc37b7ff0c04 Signed-off-by: Ninad Malwade <nmalwade@nvidia.com> Reviewed-on: http://git-master/r/1134828 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com> Reviewed-by: Matthew Pedro <mapedro@nvidia.com> 
Added kernel configurations to support
systemd functionality

boot.img size is increased by 69632 bytes

Bug 1731796

Change-Id: I4209fee15843ac645600500ed8c9fc37b7ff0c04
Signed-off-by: Ninad Malwade <nmalwade@nvidia.com>
Reviewed-on: http://git-master/r/1134828
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: Rajkumar Kasirajan <rkasirajan@nvidia.com>
Reviewed-by: Matthew Pedro <mapedro@nvidia.com>