linux-toradex.git, branch toradex_4.1-2.0.x-imx-next

imx6qdl-colibri.dtsi: UHS-I support for v1.1a hw

2019-03-21T09:49:25+00:00

Provide proper configuration for VGEN3, to make sure it's is always powered
which allows that rail to be automatically switched to 1.8 volts
for proper UHS-I operation. By default it's disabled.

With UHS-I enabled:
[  104.153898] mmc1: new ultra high speed SDR104 SDHC card at address 59b4
[  104.166202] mmcblk1: mmc1:59b4 USD00 15.0 GiB
[  104.173923]  mmcblk1: p1

root@colibri-imx6:~# hdparm -t /dev/mmcblk1
/dev/mmcblk1:
Timing buffered disk reads: 226 MB in  3.01 seconds =  75.01 MB/sec

Signed-off-by: Igor Opaniuk

ubifs: introduce Kconfig symbol for xattr support

2019-01-03T21:02:54+00:00

Allow to disable extended attribute support.

This aids in reliability testing, especially since some xattr
related bugs have surfaced.

Also an embedded system might not need it, so this allows for a
slightly smaller kernel (about 4KiB).

Signed-off-by: Stefan Agner 
Signed-off-by: Richard Weinberger 
(cherry picked from commit 7e5471ce6dba5f28a3c7afdfe168655d236f677b)

ubifs: Add CONFIG_UBIFS_FS_SECURITY to disable/enable security labels

2019-01-03T17:34:19+00:00

When write syscall is called, every time security label is searched to
determine that file's privileges should be changed.
If LSM(Linux Security Model) is not used, this is useless.

So introduce CONFIG_UBIFS_SECURITY to disable security labels. it's default
value is "y".

Signed-off-by: Hyunchul Lee 
Signed-off-by: Richard Weinberger 
(cherry picked from commit 8326c1eec2449f0e868f7b19a5fa7bfa0386ab48)

net/phy: micrel: Center FLP timing at 16ms

2018-11-06T12:03:57+00:00

The KSZ9031 defaults its FLP timing to 8ms whereas the IEEE 802.3 specification
specifiies 16ms +/-8ms.

>From the KSZ9031RNX and KSZ9031MNX data sheets revision 2.2, section
"Auto-Negotiation Timing":
	The KSZ9031[RNX or MNX] Fast Link Pulse (FLP) burst-to-burst
	transmit timing for Auto-Negotiation defaults to 8ms. IEEE 802.3
	Standard specifies this timing to be 16ms +/-8ms. Some PHY link
	partners need to receive the FLP with 16ms centered timing;
	otherwise, there can be intermittent link failures and long
	link-up times.

The PHY datasheet recommends configuring the FLP burst registers after
power-up/reset and immediately thereafter restarting auto-negotiation, so
we center the FLP timing at 16ms and then restart auto-negotiation in the
config_init for KSZ9031.

This commit consists of two upstream commits:
6270e1ae804ae781cdd3cc20eadfa4b6fb090ab7
a0da456bbf95d2a9294799bb05c61bfb24736bb7

Signed-off-by: Philippe Schenker

phy: micrel: do not use power down mode

2018-11-06T09:37:04+00:00

Some Micrel KSZ8041NL PHY chips exhibit continous RX errors after using the
power down mode bit (0.11). If the PHY is taken out of power down mode in a
certain temperature range, the PHY enters a weird state which leads to
continously reporting RX errors. In that state, the MAC is not able to receive
or send any Ethernet frames and the activity LED is constantly blinking. Since
Linux is using the suspend callback when the interface is taken down, ending up
in that state can easily happen during a normal startup.

Micrel confirmed the issue, caused by abnormal clock recovery when using power
down mode. Even the latest revision (A4, Revision ID 0x1513) seems to suffer
that problem.

Remove the suspend/resume callback to avoid using the power down mode
completely.

Signed-off-by: Stefan Agner 
Signed-off-by: Philippe Schenker

MLK-16266-01 ARM: imx: improve the soc revision calculation flow

2018-08-16T12:52:21+00:00

On our i.MX6 SOC, the DIGPROG register is used for represent the
SOC ID and silicon revision. The revision has two part: MAJOR and
MINOR. each is represented in 8 bits in the register.

  bits [15:8]: reflect the MAJOR part of the revision;
  bits [7:0]: reflect the MINOR part of the revision;

In our linux kernel, the soc revision is represented in 8 bits. MAJOR
part and MINOR each occupy 4 bits.

previous method does NOT take care about the MAJOR part in DIGPROG register.
So reformat the revision read from the HW to compatible the revision format
used in kernel.

Signed-off-by: Bai Ping 
(cherry picked from commit cf6fa1477149d4bddd096c71b46fa6c4cf9cf750)
Acked-by: Stefan Agner

imx6ull-colibri.dtsi: change touch i2c parameters

2018-07-25T13:43:06+00:00

Switch on 22 kOhm pull ups and lower the I2C frequency to around 40kHz
to get a more reliable communication.

Signed-off-by: Max Krummenacher 
(cherry picked from commit ffb2a2a59869415921e816614749ad5e48f9c077)

Revert "ARM: dts: colibri-imx7: limit eMMC SDHC frequency to 100MHz"

2018-06-19T11:01:29+00:00

Several modules have issues with HS400 at 100MHz at room temperature
but they seem to work fine at HS400 at 200MHz. Do not restrict
frequency for now.

This reverts commit 166fb4842e780f63c31622af706335e7dcd48c24.

Signed-off-by: Stefan Agner 
Acked-by: Max Krummenacher

arm: Invalidate BTB on prefetch abort outside of user mapping on Cortex A8, A9, A12 and A17

2018-06-19T10:55:52+00:00

In order to prevent aliasing attacks on the branch predictor,
invalidate the BTB on CPUs that are known to be affected when taking
a prefetch abort on a address that is outside of a user task limit.

Signed-off-by: Marc Zyngier 
Signed-off-by: Catalin Marinas 
(cherry picked from commit a07373c8c365746583f25f49fee41b1bc0ff94b2)
[jason: adapted to 4.1]
Signed-off-by: Jason Liu

arm: Add BTB invalidation on switch_mm for Cortex-A9, A12 and A17

2018-06-19T10:55:52+00:00

In order to avoid aliasing attacks against the branch predictor,
some implementations require to invalidate the BTB when switching
from one user context to another.

For this, we reuse the existing implementation for Cortex-A8, and
apply it to A9, A12 and A17.

Signed-off-by: Marc Zyngier 
Signed-off-by: Catalin Marinas 
(cherry picked commit from efcd0e857a656bbd1c1da15ff984ad6402332c61)
[jason: adapted to 4.1]
Signed-off-by: Jason Liu