linux-toradex.git, branch v2.6.30.8

Linux 2.6.30.8

2009-09-24T15:28:02+00:00

powerpc/pseries: Fix to handle slb resize across migration

2009-09-24T15:27:30+00:00

commit 46db2f86a3b2a94e0b33e0b4548fb7b7b6bdff66 upstream.

The SLB can change sizes across a live migration, which was not
being handled, resulting in possible machine crashes during
migration if migrating to a machine which has a smaller max SLB
size than the source machine. Fix this by first reducing the
SLB size to the minimum possible value, which is 32, prior to
migration. Then during the device tree update which occurs after
migration, we make the call to ensure the SLB gets updated. Also
add the slb_size to the lparcfg output so that the migration
tools can check to make sure the kernel has this capability
before allowing migration in scenarios where the SLB size will change.

BenH: Fixed #include  ->  to avoid
      breaking ppc32 build

Signed-off-by: Brian King 
Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Greg Kroah-Hartman

PCI: Unhide the SMBus on the Compaq Evo D510 USDT

2009-09-24T15:27:29+00:00

commit 6b5096e4d4496e185cd1ada5d1b8e1d941c805ed upstream.

One more form factor for Compaq Evo D510, which needs the same quirk
as the other form factors. Apparently there's no hardware monitoring
chip on that one, but SPD EEPROMs, so it's still worth unhiding the
SMBus.

Signed-off-by: Jean Delvare 
Tested-by: Nuzhna Pomoshch 
Signed-off-by: Jesse Barnes 
Signed-off-by: Greg Kroah-Hartman

libata: fix off-by-one error in ata_tf_read_block()

2009-09-24T15:27:28+00:00

commit ac8672ea922bde59acf50eaa1eaa1640a6395fd2 upstream.

ata_tf_read_block() has off-by-one error when converting CHS address
to LBA.  The bug isn't very visible because ata_tf_read_block() is
used only when generating sense data for a failed RW command and CHS
addressing isn't used too often these days.

This problem was spotted by Atsushi Nemoto.

Signed-off-by: Tejun Heo 
Reported-by: Atsushi Nemoto 
Signed-off-by: Jeff Garzik 
Signed-off-by: Greg Kroah-Hartman

virtio_blk: don't bounce highmem requests

2009-09-24T15:27:28+00:00

commit 4eff3cae9c9809720c636e64bc72f212258e0bd5 upstream

virtio_blk: don't bounce highmem requests

By default a block driver bounces highmem requests, but virtio-blk is
perfectly fine with any request that fit into it's 64 bit addressing scheme,
mapped in the kernel virtual space or not.

Besides improving performance on highmem systems this also makes the
reproducible oops in __bounce_end_io go away (but hiding the real cause).

Signed-off-by: Christoph Hellwig 
Signed-off-by: Rusty Russell 
Cc: Chuck Ebbert 
Signed-off-by: Greg Kroah-Hartman

V4L: em28xx: set up tda9887_conf in em28xx_card_setup()

2009-09-24T15:27:27+00:00

V4L: em28xx: set up tda9887_conf in em28xx_card_setup()

(cherry picked from commit ae3340cbf59ea362c2016eea762456cc0969fd9e)

Added tda9887_conf set up into em28xx_card_setup()

Signed-off-by: Franklin Meng 
Signed-off-by: Douglas Schilling Landgraf 
Signed-off-by: Mauro Carvalho Chehab 
Tested-by: Larry Finger 
Signed-off-by: Michael Krufky 
Signed-off-by: Greg Kroah-Hartman

x86, pat: Fix cacheflush address in change_page_attr_set_clr()

2009-09-24T15:27:21+00:00

commit fa526d0d641b5365676a1fb821ce359e217c9b85 upstream.

Fix address passed to cpa_flush_range() when changing page
attributes from WB to UC. The address (*addr) is
modified by __change_page_attr_set_clr(). The result is that
the pages being flushed start at the _end_ of the changed range
instead of the beginning.

This should be considered for 2.6.30-stable and 2.6.31-stable.

Signed-off-by: Jack Steiner 
Acked-by: Suresh Siddha 
Signed-off-by: H. Peter Anvin 
Signed-off-by: Greg Kroah-Hartman

x86/i386: Make sure stack-protector segment base is cache aligned

2009-09-24T15:27:21+00:00

commit 1ea0d14e480c245683927eecc03a70faf06e80c8 upstream.

The Intel Optimization Reference Guide says:

	In Intel Atom microarchitecture, the address generation unit
	assumes that the segment base will be 0 by default. Non-zero
	segment base will cause load and store operations to experience
	a delay.
		- If the segment base isn't aligned to a cache line
		  boundary, the max throughput of memory operations is
		  reduced to one [e]very 9 cycles.
	[...]
	Assembly/Compiler Coding Rule 15. (H impact, ML generality)
	For Intel Atom processors, use segments with base set to 0
	whenever possible; avoid non-zero segment base address that is
	not aligned to cache line boundary at all cost.

We can't avoid having a non-zero base for the stack-protector
segment, but we can make it cache-aligned.

Signed-off-by: Jeremy Fitzhardinge 
LKML-Reference: <4AA01893.6000507@goop.org>
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

x86: Fix x86_model test in es7000_apic_is_cluster()

2009-09-24T15:27:20+00:00

commit 005155b1f626d2b2d7932e4afdf4fead168c6888 upstream.

For the x86_model to be greater than 6 or less than 12 is
logically always true.

Signed-off-by: Roel Kluin 
Cc: Andrew Morton 
Signed-off-by: Ingo Molnar 
Signed-off-by: Greg Kroah-Hartman

sound: oxygen: work around MCE when changing volume

2009-09-24T15:27:17+00:00

commit f1bc07af9a9edc5c1d4bdd971f7099316ed2e405 upstream.

When the volume is changed continuously (e.g., when the user drags a
volume slider with the mouse), the driver does lots of I2C writes.
Apparently, the sound chip can get confused when we poll the I2C status
register too much, and fails to complete a read from it.  On the PCI-E
models, the PCI-E/PCI bridge gets upset by this and generates a machine
check exception.

To avoid this, this patch replaces the polling with an unconditional
wait that is guaranteed to be long enough.

Signed-off-by: Clemens Ladisch 
Tested-by: Johann Messner 
Signed-off-by: Takashi Iwai 
Signed-off-by: Greg Kroah-Hartman