linux-toradex.git, branch v4.9.76

Linux 4.9.76

2018-01-10T08:29:55+00:00

mtd: nand: pxa3xx: Fix READOOB implementation

2018-01-10T08:29:54+00:00

commit fee4380f368e84ed216b62ccd2fbc4126f2bf40b upstream.

In the current driver, OOB bytes are accessed in raw mode, and when a
page access is done with NDCR_SPARE_EN set and NDCR_ECC_EN cleared, the
driver must read the whole spare area (64 bytes in case of a 2k page,
16 bytes for a 512 page). The driver was only reading the free OOB
bytes, which was leaving some unread data in the FIFO and was somehow
leading to a timeout.

We could patch the driver to read ->spare_size + ->ecc_size instead of
just ->spare_size when READOOB is requested, but we'd better make
in-band and OOB accesses consistent.
Since the driver is always accessing in-band data in non-raw mode (with
the ECC engine enabled), we should also access OOB data in this mode.
That's particularly useful when using the BCH engine because in this
mode the free OOB bytes are also ECC protected.

Fixes: 43bcfd2bb24a ("mtd: nand: pxa3xx: Add driver-specific ECC BCH support")
Reported-by: Sean Nyekjær 
Tested-by: Willy Tarreau 
Signed-off-by: Boris Brezillon 
Acked-by: Ezequiel Garcia 
Tested-by: Sean Nyekjaer 
Acked-by: Robert Jarzmik 
Signed-off-by: Richard Weinberger 
Signed-off-by: Greg Kroah-Hartman

Map the vsyscall page with _PAGE_USER

2018-01-10T08:29:54+00:00

This needs to happen early in kaiser_pagetable_walk(), before the
hierarchy is established so that _PAGE_USER permission can be really
set.

A proper fix would be to teach kaiser_pagetable_walk() to update those
permissions but the vsyscall page is the only exception here so ...

Signed-off-by: Borislav Petkov 
Acked-by: Hugh Dickins 
Signed-off-by: Greg Kroah-Hartman

x86/tlb: Drop the _GPL from the cpu_tlbstate export

2018-01-10T08:29:54+00:00

commit 1e5476815fd7f98b888e01a0f9522b63085f96c9 upstream.

The recent changes for PTI touch cpu_tlbstate from various tlb_flush
inlines. cpu_tlbstate is exported as GPL symbol, so this causes a
regression when building out of tree drivers for certain graphics cards.

Aside of that the export was wrong since it was introduced as it should
have been EXPORT_PER_CPU_SYMBOL_GPL().

Use the correct PER_CPU export and drop the _GPL to restore the previous
state which allows users to utilize the cards they payed for.

As always I'm really thrilled to make this kind of change to support the
#friends (or however the hot hashtag of today is spelled) from that closet
sauce graphics corp.

Fixes: 1e02ce4cccdc ("x86: Store a per-cpu shadow copy of CR4")
Fixes: 6fd166aae78c ("x86/mm: Use/Fix PCID to optimize user/kernel switches")
Reported-by: Kees Cook 
Signed-off-by: Thomas Gleixner 
Cc: Greg Kroah-Hartman 
Cc: Peter Zijlstra 
Cc: Andy Lutomirski 
Cc: Thomas Backlund 
Signed-off-by: Greg Kroah-Hartman

parisc: qemu idle sleep support

2018-01-10T08:29:54+00:00

commit 310d82784fb4d60c80569f5ca9f53a7f3bf1d477 upstream.

Add qemu idle sleep support when running under qemu with SeaBIOS PDC
firmware.

Like the power architecture we use the "or" assembler instructions,
which translate to nops on real hardware, to indicate that qemu shall
idle sleep.

Signed-off-by: Helge Deller 
Cc: Richard Henderson 
Signed-off-by: Greg Kroah-Hartman

parisc: Fix alignment of pa_tlb_lock in assembly on 32-bit SMP kernel

2018-01-10T08:29:54+00:00

commit 88776c0e70be0290f8357019d844aae15edaa967 upstream.

Qemu for PARISC reported on a 32bit SMP parisc kernel strange failures
about "Not-handled unaligned insn 0x0e8011d6 and 0x0c2011c9."

Those opcodes evaluate to the ldcw() assembly instruction which requires
(on 32bit) an alignment of 16 bytes to ensure atomicity.

As it turns out, qemu is correct and in our assembly code in entry.S and
pacache.S we don't pay attention to the required alignment.

This patch fixes the problem by aligning the lock offset in assembly
code in the same manner as we do in our C-code.

Signed-off-by: Helge Deller 
Signed-off-by: Greg Kroah-Hartman

x86/microcode/AMD: Add support for fam17h microcode loading

2018-01-10T08:29:53+00:00

commit f4e9b7af0cd58dd039a0fb2cd67d57cea4889abf upstream.

The size for the Microcode Patch Block (MPB) for an AMD family 17h
processor is 3200 bytes.  Add a #define for fam17h so that it does
not default to 2048 bytes and fail a microcode load/update.

Signed-off-by: Tom Lendacky 
Signed-off-by: Thomas Gleixner 
Reviewed-by: Borislav Petkov 
Link: https://lkml.kernel.org/r/20171130224640.15391.40247.stgit@tlendack-t1.amdoffice.net
Signed-off-by: Ingo Molnar 
Cc: Alice Ferrazzi 
Signed-off-by: Greg Kroah-Hartman

Input: elantech - add new icbody type 15

2018-01-10T08:29:53+00:00

commit 10d900303f1c3a821eb0bef4e7b7ece16768fba4 upstream.

The touchpad of Lenovo Thinkpad L480 reports it's version as 15.

Signed-off-by: Aaron Ma 
Signed-off-by: Dmitry Torokhov 
Signed-off-by: Greg Kroah-Hartman

ARC: uaccess: dont use "l" gcc inline asm constraint modifier

2018-01-10T08:29:53+00:00

commit 79435ac78d160e4c245544d457850a56f805ac0d upstream.

This used to setup the LP_COUNT register automatically, but now has been
removed.

There was an earlier fix 3c7c7a2fc8811 which fixed instance in delay.h but
somehow missed this one as gcc change had not made its way into
production toolchains and was not pedantic as it is now !

Signed-off-by: Vineet Gupta 
Signed-off-by: Greg Kroah-Hartman

iommu/arm-smmu-v3: Cope with duplicated Stream IDs

2018-01-10T08:29:53+00:00

commit 563b5cbe334e9503ab2b234e279d500fc4f76018 upstream.

For PCI devices behind an aliasing PCIe-to-PCI/X bridge, the bridge
alias to DevFn 0.0 on the subordinate bus may match the original RID of
the device, resulting in the same SID being present in the device's
fwspec twice. This causes trouble later in arm_smmu_write_strtab_ent()
when we wind up visiting the STE a second time and find it already live.

Avoid the issue by giving arm_smmu_install_ste_for_dev() the cleverness
to skip over duplicates. It seems mildly counterintuitive compared to
preventing the duplicates from existing in the first place, but since
the DT and ACPI probe paths build their fwspecs differently, this is
actually the cleanest and most self-contained way to deal with it.

Fixes: 8f78515425da ("iommu/arm-smmu: Implement of_xlate() for SMMUv3")
Reported-by: Tomasz Nowicki 
Tested-by: Tomasz Nowicki 
Tested-by: Jayachandran C. 
Signed-off-by: Robin Murphy 
Signed-off-by: Will Deacon 
Signed-off-by: Greg Kroah-Hartman