File armada_1000_pb.pdf is not available on Marvell website anymore. So update link to webarchive where is backup copy. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
From evolution and feature point of view Armada XP belongs between Armada 370 and Armada 375 families. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Webarchive contains some useful resources like product info or links to other documents. Signed-off-by: Pali Rohár <pali@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Pull ARM SoC updates from Arnd Bergmann: "The SoC updates this time are mainly removing obsolete code from the OMAP2 platform, another step in the eternal cleanup of that platform. There are two new SoCs getting added: STMicroelectronics stm32mp13 and Microchip lan966. Both fit into existing platforms and require minimal changes here. A couple of MAINTAINER file updates relate to those changes, and update some file paths" * tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits) MAINTAINERS: Update BCM7XXX entry with additional patterns MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE ARM: SPEAr: Update MAINTAINERS entries ARM: OMAP2+: Drop unused CM defines for am3 ARM: OMAP2+: Drop unused CM and SCRM defines for omap4 ARM: OMAP2+: Drop unused CM and SCRM defines for omap5 ARM: OMAP2+: Drop unused CM defines for dra7 ARM: OMAP2+: Drop unused PRM defines for am3 ARM: OMAP2+: Drop unused PRM defines for am4 ARM: OMAP2+: Drop unused PRM defines for omap4 ARM: OMAP2+: Drop unused PRM defines for omap5 ARM: OMAP2+: Drop unused PRM defines for dra7 ARM: OMAP2+: Fix comment typo ARM: OMAP2+: Fix typo in some comments ARM: at91: add basic support for new SoC family lan966 dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards ARM: at91: Documentation: add lan966 family ARM: at91: Documentation: add sama7g5 family MAINTAINERS: add an entry for NXP S32G boards ...
STM32 SoC for v5.16, round 1
Highlights:
----------
Add support of new STM32MP13 SoC which enhances current
STM32 MPU family. It is mainly a derivative of STM32MP15 SoCs
(one Cortex-A7 plus standard peripherals).
The STM32MP13 SoC diversity is composed by:
-STM32MP131:
-core: 1*CA7, 17*TIMERS, 5*LPTIMERS, DMA/MDMA/DMAMUX
-storage: 3*SDMCC, 1*QSPI, FMC
-com: USB (OHCI/EHCI, OTG), 5*I2C, 5*SPI/I2S, 8*U(S)ART
-audio: 2*SAI
-network: 1*ETH(GMAC)
-STM32MP133: STM32MP131 + 2*CAN, ETH2(GMAC), ADC1
-STM32MP135: STM32MP133 + DCMIPP, LTDC
* tag 'stm32-soc-for-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: stm32: add initial support for STM32MP13 family
docs: arm: stm32: introduce STM32MP13 SoCs
Link: https://lore.kernel.org/r/0b6c9657-dcca-3bad-601f-610dfc81d9ae@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add the new LAN966 ARMv7 based SoC family from Microchip. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> [nicolas.ferre@microchip.com: move entry as part of new Cortex-A7 core type] Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211004105926.5696-3-kavyasree.kotagiri@microchip.com
Add the new SAMA7G5 ARMv7 based SoC family from Microchip to the AT91 documentation. Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20210704181110.9254-1-pali@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Marvell put CN913x into Octeon TX2 family but they are different from all other Octeon TX2 products. Instead CN913x is evolution from Armada 7k/8k products. Signed-off-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20210919143348.24338-1-pali@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Pali Rohár <pali@kernel.org> Link: https://lore.kernel.org/r/20210919143327.24289-1-pali@kernel.org Signed-off-by: Jonathan Corbet <corbet@lwn.net>