linux-toradex.git/Documentation/devicetree/bindings/arm/msm, branch v4.2.3 Linux kernel for Apalis and Colibri modules Merge git://www.linux-watchdog.org/linux-watchdog 2015-04-22T18:22:55+00:00 Linus Torvalds torvalds@linux-foundation.org 2015-04-22T18:22:55+00:00 7dcca3e92a34bf8ffdc4c01a49182ce1cb6ff534 Pull watchdog updates from Wim Van Sebroeck: "This contains following changes: - Octeon: convert to watchdog-API and apply some fixes - Cadence wdt: remove dependency on ARCH - add DT bindings for qcom + msm - bcm281xx: Remove use of seq_printf return value - stmp3xxx_rtc_wdt + pnx4008_wdt: fix broken email addresses" * git://www.linux-watchdog.org/linux-watchdog: watchdog: stmp3xxx_rtc_wdt: fix broken email address watchdog: pnx4008_wdt: fix broken email address watchdog: octeon: use fixed length string for register names watchdog: octeon: fix some trivial coding style issues watchdog: octeon: convert to WATCHDOG_CORE API watchdog: cadence: Remove Kconfig dependency on ARCH ARM: msm: add watchdog entries to DT timer binding doc ARM: qcom: add description of KPSS WDT for IPQ8064 watchdog: qcom: use timer devicetree binding watchdog: bcm281xx: Remove use of seq_printf return value 
Pull watchdog updates from Wim Van Sebroeck:
 "This contains following changes:

   - Octeon: convert to watchdog-API and apply some fixes
   - Cadence wdt: remove dependency on ARCH
   - add DT bindings for qcom + msm
   - bcm281xx: Remove use of seq_printf return value
   - stmp3xxx_rtc_wdt + pnx4008_wdt: fix broken email addresses"

* git://www.linux-watchdog.org/linux-watchdog:
  watchdog: stmp3xxx_rtc_wdt: fix broken email address
  watchdog: pnx4008_wdt: fix broken email address
  watchdog: octeon: use fixed length string for register names
  watchdog: octeon: fix some trivial coding style issues
  watchdog: octeon: convert to WATCHDOG_CORE API
  watchdog: cadence: Remove Kconfig dependency on ARCH
  ARM: msm: add watchdog entries to DT timer binding doc
  ARM: qcom: add description of KPSS WDT for IPQ8064
  watchdog: qcom: use timer devicetree binding
  watchdog: bcm281xx: Remove use of seq_printf return value
ARM: msm: add watchdog entries to DT timer binding doc 2015-04-22T13:28:16+00:00 Mathieu Olivari mathieu@codeaurora.org 2015-02-21T02:19:36+00:00 cf79fb14d09f8a9aaadfce59d01cfedf4f96d99d The watchdog has been reworked to use the same DT node as the timer. This change is updating the device tree doc accordingly. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be> 
The watchdog has been reworked to use the same DT node as the timer.
This change is updating the device tree doc accordingly.

Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
devicetree: bindings: Document qcom,idle-states 2015-04-03T20:33:51+00:00 Lina Iyer lina.iyer@linaro.org 2015-03-25T20:25:28+00:00 52cd8451818bffa25bec2f69bc6286b3cc045bf7 Document cpuidle states of QCOM cpus. In addition to arm-idle-state compatible string, the ARM idle state definition must define one of the following compatible strings - "qcom,idle-state-ret", "qcom,idle-state-spc", "qcom,idle-state-pc", The compatibles helps the SPM platform driver to use the correct idle function when the index to the idle state is passed to the platform driver. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net> 
Document cpuidle states of QCOM cpus. In addition to arm-idle-state
compatible string, the ARM idle state definition must define one of the
following compatible strings -
	"qcom,idle-state-ret",
	"qcom,idle-state-spc",
	"qcom,idle-state-pc",

The compatibles helps the SPM platform driver to use the correct idle
function when the index to the idle state is passed to the platform
driver.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
devicetree: bindings: Update qcom,saw2 node bindings 2015-04-03T20:33:51+00:00 Lina Iyer lina.iyer@linaro.org 2015-03-25T20:25:27+00:00 005c5dc9b3dd72970992d05ea63f1148d020112c Update qcom,saw2 node bindings with compatible strings to identify nodes that provides cpuidle functionality for a particular SoC. Remove unused compatible strings. Update examples for different SAW nodes. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net> 
Update qcom,saw2 node bindings with compatible strings to identify nodes
that provides cpuidle functionality for a particular SoC. Remove
unused compatible strings.

Update examples for different SAW nodes.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Documentation: devicetree: Fix double words in Doumentation/devicetree 2015-01-28T22:13:11+00:00 Masanari Iida standby24x7@gmail.com 2015-01-02T13:54:39+00:00 ac3e8ea1d3a6b204f78e2e828f85b15d25617515 This patch fix multiple words such as "the the" and "which which" in Documentation/devicetree. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net> 
This patch fix multiple words such as "the the" and "which which"
in Documentation/devicetree.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
devicetree: bindings: Document qcom,saw2 node 2014-02-11T21:00:39+00:00 Stephen Boyd sboyd@codeaurora.org 2013-11-01T01:20:30+00:00 4c6ede21cd0d4df0c68d4203fa63bb17e29d2e93 The saw2 binding describes the SPM/AVS wrapper hardware used to control the regulator supplying voltage to the Krait CPUs. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> 
The saw2 binding describes the SPM/AVS wrapper hardware used to
control the regulator supplying voltage to the Krait CPUs.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
devicetree: bindings: Document qcom,kpss-acc 2014-02-11T21:00:38+00:00 Stephen Boyd sboyd@codeaurora.org 2013-11-01T01:20:30+00:00 007290cb3db0bba6a7f441b3dc849b365b0d54b1 The kpss acc binding describes the clock, reset, and power domain controller for a Krait CPU. Cc: <devicetree@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> 
The kpss acc binding describes the clock, reset, and power domain
controller for a Krait CPU.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 2013-05-02T16:31:45+00:00 Linus Torvalds torvalds@linux-foundation.org 2013-05-02T16:31:45+00:00 97b1007a2924aaa9126398623f6755a8c3c6a616 Pull ARM SoC platform updates from Olof Johansson: "This branch contains part 1 of the platform updates for 3.10. Among the highlights: - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3) - New support for CSR SiRFatlas6 SoCs - A handful of updates for NVidia T114 (a.k.a. Tegra 4) - A bunch of updates for the shmobile platforms - A handful of updates for davinci - A few updates for Qualcomm MSM - Plus a handful of other patches, defconfig updates, etc." * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits) ARM: tegra: pm: fix build error w/o PM_SLEEP ARM: davinci: ensure global variables are declared ARM: davinci: sram.c: fix incorrect type in assignment ARM: davinci: da8xx dt: make file local symbols static ARM: davinci: da8xx: add remoteproc support ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries ARM: socfpga: Add clock entries into device tree ARM: socfpga: Enable soft reset ARM: EXYNOS: replace cpumask by the corresponding macro ARM: EXYNOS: handle properly the return values ARM: EXYNOS: factor out the idle states ARM: OMAP4: Enable fix for Cortex-A9 erratas ARM: OMAP2+: Export SoC information to userspace ARM: OMAP2+: SoC name and revision unification ARM: OMAP2+: Move common part of late init into common function ARM: tegra: pm: remove duplicated include from pm.c ARM: davinci: da850: override mmc DT node device name ARM: davinci: da850: add mmc DT entries mmc: davinci_mmc: add DT support ARM: SAMSUNG: check processor type before cache restoration in resume ... 
Pull ARM SoC platform updates from Olof Johansson:
 "This branch contains part 1 of the platform updates for 3.10.  Among
  the highlights:

   - Support for the new Atmel Cortex-A5 based platforms (SAMA5D3)
   - New support for CSR SiRFatlas6 SoCs
   - A handful of updates for NVidia T114 (a.k.a. Tegra 4)
   - A bunch of updates for the shmobile platforms
   - A handful of updates for davinci
   - A few updates for Qualcomm MSM
   - Plus a handful of other patches, defconfig updates, etc."

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (135 commits)
  ARM: tegra: pm: fix build error w/o PM_SLEEP
  ARM: davinci: ensure global variables are declared
  ARM: davinci: sram.c: fix incorrect type in assignment
  ARM: davinci: da8xx dt: make file local symbols static
  ARM: davinci: da8xx: add remoteproc support
  ARM: socfpga: Upgrade clk driver for socfpga to make use of dts clock entries
  ARM: socfpga: Add clock entries into device tree
  ARM: socfpga: Enable soft reset
  ARM: EXYNOS: replace cpumask by the corresponding macro
  ARM: EXYNOS: handle properly the return values
  ARM: EXYNOS: factor out the idle states
  ARM: OMAP4: Enable fix for Cortex-A9 erratas
  ARM: OMAP2+: Export SoC information to userspace
  ARM: OMAP2+: SoC name and revision unification
  ARM: OMAP2+: Move common part of late init into common function
  ARM: tegra: pm: remove duplicated include from pm.c
  ARM: davinci: da850: override mmc DT node device name
  ARM: davinci: da850: add mmc DT entries
  mmc: davinci_mmc: add DT support
  ARM: SAMSUNG: check processor type before cache restoration in resume
  ...
SSBI: Convert SSBI to device tree 2013-03-25T17:39:40+00:00 David Brown davidb@codeaurora.org 2013-03-12T18:41:50+00:00 97f00f7120fe3396302693cdc4b1d11bbacad963 The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs using it will be using device tree. Convert this driver to indentify with device tree. This makes the bus probing a good bit simpler, since the attaching of child nodes can be represented directly in the devicetree, rather than having to be inferred by name. Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
The SSBI bus is exclusive to the Qualcomm MSM targets, and all SoCs
using it will be using device tree.  Convert this driver to indentify
with device tree.

This makes the bus probing a good bit simpler, since the attaching of
child nodes can be represented directly in the devicetree, rather than
having to be inferred by name.

Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
ARM: msm: Rework timer binding to be more general 2013-03-22T17:46:16+00:00 Stephen Boyd sboyd@codeaurora.org 2013-03-15T03:31:38+00:00 eebdb0c1e1d63532399f7cbb65ade5969d63df06 The msm timer binding I wrote is bad. First off, the clock frequency in the binding for the dgt is wrong. Software divides down the input rate by 4 to achieve the rate listed in the binding. We also treat each individual timer as a separate hardware component, when in reality there is one timer block (that may be duplicated per cpu) with multiple timers within it. Depending on the version of the hardware there can be one or two general purpose timers, status and divider control registers, and an entirely different register layout. In the next patch we'll need to know about the different register layouts so that we can properly check the status register after clearing the count. The current binding makes this complicated because the general purpose timer's reg property doesn't indicate where that status register is, and in fact it is beyond the size of the reg property. Clean all this up by just having one node for the timer hardware, and describe all the interrupts and clock frequencies supported while having one reg property that covers the entire timer register region. We'll use the compatible field in the future to determine different register layouts and if we should read the status registers, etc. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> 
The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.

In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.

Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>