linux-toradex.git/Documentation/devicetree/bindings/clock/sunxi.txt, branch v4.3.1

clk: sunxi: Add support for the usb-clk on sun8i a23 and a33 SoCs

2015-06-02T08:24:39+00:00

The usb-clk on sun8i a23 and a33 SoCs is similar to the ones found
on sun6i-a31 SoCs but instead of a 3th phy the a23 / a33 have a hsic
interface which gets enabled by almost the same bits as used on
the a31 for the 3rd phy, but not exactly the same bits so we need
a new compatible for this.

Signed-off-by: Hans de Goede 
Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai

clk: sunxi: Add muxable ahb factors clock for sun5i and sun7i

2015-03-21T10:48:40+00:00

The AHB clock on sun5i and sun7i are muxable divider clocks.
Use a factors clock to support them.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add support for sun9i A80 USB clocks and resets

2015-02-23T08:25:54+00:00

The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller. Also, access to the address block is controlled by a
clock gate to AHB.

Add support for resets requiring a clock to be enabled when
asserting/deasserting the reset controls, and add the sun9i USB
clocks.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add driver for A80 MMC config clocks/resets

2015-01-20T16:14:38+00:00

On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Add mod0 and mmc module clock support for A80

2015-01-19T21:48:55+00:00

The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Rework MMC phase clocks

2015-01-14T09:39:16+00:00

Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard 
Reviewed-by: Chen-Yu Tsai 
Tested-by: Chen-Yu Tsai 
Acked-by: Mike Turquette

clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

2014-12-21T22:51:37+00:00

This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output

2014-11-23T16:02:56+00:00

Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver

2014-11-23T16:02:56+00:00

This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.

Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard

clk: sunxi: unify APB1 clock

2014-11-11T14:54:40+00:00

This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.

Signed-off-by: Emilio López 
[wens@csie.org: Add mux mask bits]
Signed-off-by: Chen-Yu Tsai 
Signed-off-by: Maxime Ripard