linux-toradex.git/Documentation/devicetree/bindings/clock/ti/davinci, branch master Linux kernel for Apalis and Colibri modules dt-bindings: Fix typo in comment 2022-07-21T19:14:27+00:00 Slark Xiao slark_xiao@163.com 2022-07-21T01:17:46+00:00 12e5bde18d7f6ca4ee5fbd7c6f060d0674bf3237 Fix typo in the comment Signed-off-by: Slark Xiao <slark_xiao@163.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220721011746.19663-1-slark_xiao@163.com 
Fix typo in the comment

Signed-off-by: Slark Xiao <slark_xiao@163.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220721011746.19663-1-slark_xiao@163.com
dt-bindings: power: Convert Generic Power Domain bindings to json-schema 2019-11-14T16:46:16+00:00 Krzysztof Kozlowski krzk@kernel.org 2019-10-30T17:32:15+00:00 5279a3d8bedea477eaaaddedc3dd5fa62b86cfd7 Convert Generic Power Domain bindings to DT schema format using json-schema. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> 
Convert Generic Power Domain bindings to DT schema format using
json-schema.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: clock: Add bindings for DA8XX CFGCHIP clocks 2018-03-20T17:16:26+00:00 David Lechner david@lechnology.com 2018-03-16T02:52:33+00:00 0c92c71770457df9c5459190ba72350459785f37 This adds a new binding for the clocks present in the CFGCHIP syscon registers in TI DA8XX SoCs. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This adds a new binding for the clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock: New bindings for TI Davinci PSC 2018-03-20T17:16:26+00:00 David Lechner david@lechnology.com 2018-03-16T02:52:25+00:00 21cdf7269f9dcd8dc22d152fbfee85e4ea57289f This adds a new binding for the Power Sleep Controller (PSC) for the mach-davinci family of processors. Note: Although TI Keystone has a very similar PSC, we are not using the existing bindings. Keystone is using a legacy one-node-per-clock binding (actually two nodes if you count the separate reset binding for the same IP block). Also, some davinci LPSCs have quirks that aren't handled by the keystone bindings, so we would be adding one compatible string per clock with quirks instead of just a new compatible string for each controller. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This adds a new binding for the Power Sleep Controller (PSC) for the
mach-davinci family of processors.

Note: Although TI Keystone has a very similar PSC, we are not using the
existing bindings. Keystone is using a legacy one-node-per-clock binding
(actually two nodes if you count the separate reset binding for the same
IP block). Also, some davinci LPSCs have quirks that aren't handled by
the keystone bindings, so we would be adding one compatible string per
clock with quirks instead of just a new compatible string for each
controller.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock: Add new bindings for TI Davinci PLL clocks 2018-03-20T16:33:08+00:00 David Lechner david@lechnology.com 2018-03-16T02:52:17+00:00 b6e37ce2371dac0d696332d8e74c110030ab47c3 This adds a new binding for the PLL IP blocks in the mach-davinci family of processors. Currently, only da850 has device tree support but these bindings can also work for other SoCs in this family just by adding new compatible strings. Note: Although these PLL controllers are very similar to the TI Keystone SoCs, we are not re-using those bindings. The Keystone bindings use a legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs have a slightly different PLL register layout and a number of quirks that can't be handled by the existing bindings, so the keystone bindings could not be used as-is anyway. Signed-off-by: David Lechner <david@lechnology.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This adds a new binding for the PLL IP blocks in the mach-davinci
family of processors. Currently, only da850 has device tree support
but these bindings can also work for other SoCs in this family just
by adding new compatible strings.

Note: Although these PLL controllers are very similar to the TI Keystone
SoCs, we are not re-using those bindings. The Keystone bindings use a
legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
have a slightly different PLL register layout and a number of quirks
that can't be handled by the existing bindings, so the keystone bindings
could not be used as-is anyway.

Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>