linux-toradex.git/Documentation/devicetree/bindings/clock, branch master Linux kernel for Apalis and Colibri modules Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2026-10-30T16:18:43+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-10-30T16:18:43+00:00 4517b5a6c8745f244d89971dc34ec69f5a9eb3d5 Pull clk updates from Stephen Boyd: "Here's the clk changes for the merge window which is dominated in the diffstat by Qualcomm churning out new SoCs that need clk drivers. Looking beyond the sheer amount of lines of mostly data there we have a clk nexus DT binding change in the core clk framework and a driver core patch to add a subsys driver macro. The clock nexus support is useful for devices that map clks internally or for connectors on a board that route clock signals to another board. I suspect the use of this will expand in the future, so we have unit tests to make sure it doesn't break. The driver core change adds subsys_driver() and subsys_platform_driver() so we can register early drivers without open-coding that all (module_platform_driver() is at device initcall level so it isn't be used). Beyond the core framework bits we have lots of changes all over the tree to initialize 'struct clk_init_data'. The potential risk here is that someone forgets to initialize all the members of that structure and either the clk flags cause weird behavior later on or the parents are pointing at junk and the clk is orphaned forever. The patches just initialize the thing with zeroes to be safe. Longer term we should probably move this struct out of 'struct clk_hw' and pass it during clk registration time. That's a much bigger change and would require restructuring entire drivers that rely on the pointer being there. Finally, we have the usual fixes like calculation updates for dividers, handling error paths during clk registration, or fixing clk data now that drivers are using them. Those patches are dwarfed by the amount of new SoC support and only affect those SoCs and the consumers of those clks. Overall I'm more concerned the clk_init_data patches are going to expose some latent bugs that we didn't notice before because something was relying on clks being orphaned and now they're not. Core: - subsys_driver() / subsys_platform_driver() macros - Clock nexus DT binding support (with KUnit tests) - Spread-spectrum configuration validation - Fully initialize struct clk_init_data across many drivers New Drivers: - Anlogic DR1V90 CRU - ZTE zx297520v3 top, matrix, and LSP clocks - Samsung Exynos5515 and ACPM driver extended to Exynos850. - Qualcomm Eliza camera, camera-BIST, GPU, and video clks - Qualcomm Hawi / Maili camera and GPU controllers - Qualcomm Kuno global, RPMh - Qualcomm MSM8952 global, RPM - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets - Qualcomm IPQ5210 / IPQ9650 network clocks - i.MX93 350 MHz fractional-N GP-PLL for display - i.MX pll14xx spread-spectrum clock generation - Amlogic A9 SCMI clock controller - Allwinner single-divider "update bit" support - EN7523 Serdes port selection" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ... 
Pull clk updates from Stephen Boyd:
 "Here's the clk changes for the merge window which is dominated in the
  diffstat by Qualcomm churning out new SoCs that need clk drivers.

  Looking beyond the sheer amount of lines of mostly data there we have
  a clk nexus DT binding change in the core clk framework and a driver
  core patch to add a subsys driver macro.

  The clock nexus support is useful for devices that map clks internally
  or for connectors on a board that route clock signals to another
  board. I suspect the use of this will expand in the future, so we have
  unit tests to make sure it doesn't break.

  The driver core change adds subsys_driver() and
  subsys_platform_driver() so we can register early drivers without
  open-coding that all (module_platform_driver() is at device initcall
  level so it isn't be used).

  Beyond the core framework bits we have lots of changes all over the
  tree to initialize 'struct clk_init_data'. The potential risk here is
  that someone forgets to initialize all the members of that structure
  and either the clk flags cause weird behavior later on or the parents
  are pointing at junk and the clk is orphaned forever. The patches just
  initialize the thing with zeroes to be safe. Longer term we should
  probably move this struct out of 'struct clk_hw' and pass it during
  clk registration time. That's a much bigger change and would require
  restructuring entire drivers that rely on the pointer being there.

  Finally, we have the usual fixes like calculation updates for
  dividers, handling error paths during clk registration, or fixing clk
  data now that drivers are using them. Those patches are dwarfed by the
  amount of new SoC support and only affect those SoCs and the consumers
  of those clks. Overall I'm more concerned the clk_init_data patches
  are going to expose some latent bugs that we didn't notice before
  because something was relying on clks being orphaned and now they're
  not.

  Core:
   - subsys_driver() / subsys_platform_driver() macros
   - Clock nexus DT binding support (with KUnit tests)
   - Spread-spectrum configuration validation
   - Fully initialize struct clk_init_data across many drivers

  New Drivers:
   - Anlogic DR1V90 CRU
   - ZTE zx297520v3 top, matrix, and LSP clocks
   - Samsung Exynos5515 and ACPM driver extended to Exynos850.
   - Qualcomm Eliza camera, camera-BIST, GPU, and video clks
   - Qualcomm Hawi / Maili camera and GPU controllers
   - Qualcomm Kuno global, RPMh
   - Qualcomm MSM8952 global, RPM
   - Qualcomm Nord camera/video clocks, EMAC interconnect, PHY resets
   - Qualcomm IPQ5210 / IPQ9650 network clocks
   - i.MX93 350 MHz fractional-N GP-PLL for display
   - i.MX pll14xx spread-spectrum clock generation
   - Amlogic A9 SCMI clock controller
   - Allwinner single-divider "update bit" support
   - EN7523 Serdes port selection"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (316 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...
Merge branches 'clk-renesas', 'clk-samsung', 'clk-starfive', 'clk-tenstorrent' and 'clk-pile' into clk-next 2026-10-26T23:48:58+00:00 Brian Masney bmasney@redhat.com 2026-10-26T23:48:58+00:00 0d9678b125d8315d62de1261bee67c7e6f21457e * clk-renesas: (25 commits) clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS clk: renesas: rzg2l: Fix internal clock names clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets clk: renesas: Add support for RZ/G2M v3.0 clk: renesas: r9a08g046: Add CANFD clocks and resets clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions clk: renesas: r8a779g0: Add ZG clocks clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z() clk: renesas: r9a09g077: Register SYSC regmap clk: renesas: rcar-gen3: Use FIELD_GET() clk: renesas: rzv2h: Convert to clk_hw based provider API clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register() clk: renesas: r9a08g046: Add PCIe clocks and reset clk: renesas: Make sure clk_init_data is fully initialized clk: renesas: r9a08g046: Add clock and reset entries for LVDS clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries clk: renesas: r9a08g046: Sort macro definitions alphabetically clk: renesas: rzg2l: Add support for RZ/G3L DSI mux clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle ... * clk-samsung: clk: samsung: acpm: add Exynos850 support clk: samsung: acpm: introduce driver data for SoC-specific clocks clk: samsung: Introduce Exynos5515 clock driver clk: samsung: clk-pll: Add support for pll_309 dt-bindings: clock: Add Exynos5515 SoC * clk-starfive: dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator * clk-tenstorrent: MAINTAINERS: Update RISC-V Tenstorrent SoC entry clk: tenstorrent: use regmap_assign_bits() for conditional set/clear clk: tenstorrent: Fix refcount leak on shared gate clk enable failure clk: tenstorrent: Assign .num before accessing .hws * clk-pile: (126 commits) clk: imx: pll14xx: support spread spectrum clock generation clk: cdce925: Size the PLL child name buffer for any int clk: stm32: fix clock array size for STM32MP21 dt-bindings: clock: Convert HiSilicon clocks to DT schema clk: lmk04832: Handle reset GPIO lookup errors dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional clk: tegra: bpmp: remove kcalloc clk: mmp2-audio: add missing PM_CLK dependency clk: zte: Introduce a driver for zx297520v3 LSP clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Add zx PLL support infrastructure clk: zte: Add regmap-based clocks clk: zte: Add Clock registration infrastructure dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define ... 
* clk-renesas: (25 commits)
  clk: renesas: r8a78000: Add SGASYNCD8_PERW_BUS
  clk: renesas: rzg2l: Fix internal clock names
  clk: renesas: r9a08g046: Add TSU and ADC1 clocks and resets
  clk: renesas: Add support for RZ/G2M v3.0
  clk: renesas: r9a08g046: Add CANFD clocks and resets
  clk: renesas: r9a08g046: Propagate clk rate for ETH TX mux clocks
  dt-bindings: clock: Add r8a774a3 CPG Core Clock definitions
  clk: renesas: r8a779g0: Add ZG clocks
  clk: renesas: rcar-gen4: Tidy up DEF_GEN4_Z()
  clk: renesas: r9a09g077: Register SYSC regmap
  clk: renesas: rcar-gen3: Use FIELD_GET()
  clk: renesas: rzv2h: Convert to clk_hw based provider API
  clk: renesas: rzv2h: Drop duplicated parent lookup in fixed_mod_status_clk_register()
  clk: renesas: r9a08g046: Add PCIe clocks and reset
  clk: renesas: Make sure clk_init_data is fully initialized
  clk: renesas: r9a08g046: Add clock and reset entries for LVDS
  clk: renesas: r9a08g046: Add MIPI DSI and LCDC clock/reset entries
  clk: renesas: r9a08g046: Sort macro definitions alphabetically
  clk: renesas: rzg2l: Add support for RZ/G3L DSI mux
  clk: renesas: rzg2l: Add support for LVDS fixed-factor divider with 4:7 duty cycle
  ...

* clk-samsung:
  clk: samsung: acpm: add Exynos850 support
  clk: samsung: acpm: introduce driver data for SoC-specific clocks
  clk: samsung: Introduce Exynos5515 clock driver
  clk: samsung: clk-pll: Add support for pll_309
  dt-bindings: clock: Add Exynos5515 SoC

* clk-starfive:
  dt-bindings: soc: starfive: Add StarFive JHB100 syscon modules
  dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
  dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator

* clk-tenstorrent:
  MAINTAINERS: Update RISC-V Tenstorrent SoC entry
  clk: tenstorrent: use regmap_assign_bits() for conditional set/clear
  clk: tenstorrent: Fix refcount leak on shared gate clk enable failure
  clk: tenstorrent: Assign .num before accessing .hws

* clk-pile: (126 commits)
  clk: imx: pll14xx: support spread spectrum clock generation
  clk: cdce925: Size the PLL child name buffer for any int
  clk: stm32: fix clock array size for STM32MP21
  dt-bindings: clock: Convert HiSilicon clocks to DT schema
  clk: lmk04832: Handle reset GPIO lookup errors
  dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional
  clk: tegra: bpmp: remove kcalloc
  clk: mmp2-audio: add missing PM_CLK dependency
  clk: zte: Introduce a driver for zx297520v3 LSP clocks
  clk: zte: Introduce a driver for zx297520v3 matrix clocks
  clk: zte: Introduce a driver for zx297520v3 top clocks
  clk: zte: Add zx PLL support infrastructure
  clk: zte: Add regmap-based clocks
  clk: zte: Add Clock registration infrastructure
  dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller
  dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller
  clk: nuvoton: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Add missing WDT/WWDT parent clocks
  dt-bindings: clock: ma35d1: Drop CLK_MAX_IDX define
  ...
dt-bindings: clock: Convert HiSilicon clocks to DT schema 2026-10-26T23:45:51+00:00 Rob Herring (Arm) robh@kernel.org 2026-10-01T21:20:48+00:00 bb1d071a54fefaa43161368f34d8dd13f1720531 Convert the HiSilicon Hi6220/Hi3660/Hi3670 clock bindings to DT schema format. Rearrange the binding documents splitting out the stub clock binding from everything else. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Wei Xu <xuwei5@hisilicon.com> Link: https://patch.msgid.link/20261001212051.2227941-1-robh@kernel.org Signed-off-by: Brian Masney <bmasney@redhat.com> 
Convert the HiSilicon Hi6220/Hi3660/Hi3670 clock bindings to DT schema
format. Rearrange the binding documents splitting out the stub clock
binding from everything else.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Link: https://patch.msgid.link/20261001212051.2227941-1-robh@kernel.org
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clock: anlogic,dr1v90-cru: make external clocks optional 2026-10-26T23:45:50+00:00 Junhui Liu junhui.liu@pigmoral.tech 2026-10-02T16:28:39+00:00 fcfe685cde2f49fe6195b62cdbcaa1c906a853ae The main oscillator is the only required input clock for the CRU, while the external CAN and WDT clocks are optional board-level inputs. The binding currently requires all three clocks, forcing device trees for boards without these external inputs to add stub fixed-clock nodes for which no meaningful clock-frequency can be specified. Allow the clocks and clock-names properties to contain just "osc", optionally followed by either or both of "can_ext" and "wdt_ext". Fixes: 155d900e4c7d ("dt-bindings: clock: add Anlogic DR1V90 CRU") Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
The main oscillator is the only required input clock for the CRU, while
the external CAN and WDT clocks are optional board-level inputs. The
binding currently requires all three clocks, forcing device trees for
boards without these external inputs to add stub fixed-clock nodes for
which no meaningful clock-frequency can be specified.

Allow the clocks and clock-names properties to contain just "osc",
optionally followed by either or both of "can_ext" and "wdt_ext".

Fixes: 155d900e4c7d ("dt-bindings: clock: add Anlogic DR1V90 CRU")
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:13:31+00:00 244539a22fbd11e18dbcbc02453e0f07f1a6368c The clock controller of the zx297520v3 Low Speed Peripherals is relatively clean. One register per device with gates, muxes and resets and for some devices a divider. There are even bits in the matrix controller to control propagation of clock lines down to LSP. The clocks are sorted by register address and I am convinced that the device list is complete. There are, however, a few more registers that are likely extra dividers for TDM and I2S devices. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
The clock controller of the zx297520v3 Low Speed Peripherals is
relatively clean. One register per device with gates, muxes and resets
and for some devices a divider. There are even bits in the matrix
controller to control propagation of clock lines down to LSP.

The clocks are sorted by register address and I am convinced that the
device list is complete. There are, however, a few more registers that
are likely extra dividers for TDM and I2S devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:50:55+00:00 574e62ac2dd913774486b09ff2672be872f23aed This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. I don't know much about the hwlocks yet other than that they exist, so there is no header yet adding meaning to their indices. Presumably that meaning doesn't exist in hardware and is de facto defined by ZTE's firmware blobs running on the rprocs. The zte-zx297520v3-crm driver will instantiate separate MFD children for clocks and resets, which are handled by separate clock and reset drivers. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
This controller contains clocks and resets for high speed devices on the
zx297520v3 board and hardware spinlocks that I expect will be necessary
to communicate correctly with the LTE DSP firmware blob.

I don't know much about the hwlocks yet other than that they exist, so
there is no header yet adding meaning to their indices. Presumably that
meaning doesn't exist in hardware and is de facto defined by ZTE's
firmware blobs running on the rprocs.

The zte-zx297520v3-crm driver will instantiate separate MFD children for
clocks and resets, which are handled by separate clock and reset
drivers.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller 2026-10-26T23:45:49+00:00 Stefan Dösinger stefandoesinger@gmail.com 2026-09-27T20:13:29+00:00 7bdc3c32d5037f9d55c5f109e29f0c2c066ba522 These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. Clocks go from oscillator -> top -> matrix -> LSP, with a register in top controlling most clocks that get passed to matrix and a register in matrix controlling all the clocks that get passed to LSP. Generally every device has two clocks (one work clock, and one that connects it to the bus, I call it PCLK), two reset bits (I don't know what the difference is - sometimes asserting one is enough to reset the device, sometimes both need to be asserted). PCLK and WCLK are controlled by individual gates. Some devices have a mux and/or a divider for their work clock. Some devices, like the GPIO controller, only have reset bits and no clocks. The top clock controller is fed by a 26 MHz external oscillator and has 4 PLLs to generate other clock rates. ZTE's kernel mostly relies on the boot ROM to set up PLLs, but one LTE-related PLL is not configured on some boards. Therefore my driver contains code to program PLLs. It produces identical settings as the boot ROM for the pre-programmed frequencies. Not all clocks will have an explicit user in the end. I am defining a lot of them simply to shut them off. The boot loader sets up a few of the proprietary timers, which will send regular IRQs (although the kernel of course doesn't need to listen to them). I don't plan to add a driver for the proprietary timer as I see no use for them - the ARM arch timer works just fine. I will add a driver for the very similar proprietary watchdog though. The clock list in this patch is pretty complete but not exhaustive. There are other bits that are enabled, but I couldn't deduce what they are controlling by trial and error. Some of them seem to do nothing. Others cause an instant hang of the board when disabled. It is quite likely that a handful more clocks will be added in the future, but not a large number. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
These SoCs have 3 clock and reset controllers: Top, Matrix and LSP.
Clocks go from oscillator -> top -> matrix -> LSP, with a register in
top controlling most clocks that get passed to matrix and a register in
matrix controlling all the clocks that get passed to LSP.

Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.

The top clock controller is fed by a 26 MHz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.

Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.

The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
dt-bindings: clock: ma35d1: Document the missing crystal inputs 2026-10-26T23:45:48+00:00 Miquel Raynal miquel.raynal@bootlin.com 2026-09-30T17:24:48+00:00 ea1f41802312e77b58113146a060fb0546b2234d The MA35D1 clock controller takes two crystal oscillator inputs from the board: - HXT, a high-speed 24 MHz crystal for most of the system - LXT, a low-speed 32.768 kHz crytal for the RTC and low power modes So far the binding was expecting a single crystal. The example named it HXT, but no real definition for it was given. LXT was not even described. In order to remain backward compatible, we will continue to allow either one (HXT) or two (HXT then LXT) input clocks. I propose to give those phandles a name to clarify what these entries expect, but I'm not listing the clock-names property in the required block, for backward compatibility. The rates are fixed by the TRM, so even if the second oscillator is not described, the OS can make an educated guess. Fixes: 2f8b5eb589cb ("dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller") Cc: stable@vger.kernel.org Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-2-48937ee6c9bb@bootlin.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Brian Masney <bmasney@redhat.com> 
The MA35D1 clock controller takes two crystal oscillator inputs from
the board:
- HXT, a high-speed 24 MHz crystal for most of the system
- LXT, a low-speed 32.768 kHz crytal for the RTC and low power modes

So far the binding was expecting a single crystal. The example named it
HXT, but no real definition for it was given. LXT was not even
described. In order to remain backward compatible, we will continue to
allow either one (HXT) or two (HXT then LXT) input clocks. I propose to
give those phandles a name to clarify what these entries expect, but I'm
not listing the clock-names property in the required block, for backward
compatibility. The rates are fixed by the TRM, so even if the second
oscillator is not described, the OS can make an educated guess.

Fixes: 2f8b5eb589cb ("dt-bindings: clock: nuvoton: add binding for ma35d1 clock controller")
Cc: stable@vger.kernel.org
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://patch.msgid.link/20260930-perso-ma35d1-upstream-clk-v6-2-48937ee6c9bb@bootlin.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Brian Masney <bmasney@redhat.com>
Merge tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2026-10-25T06:11:23+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-10-25T06:11:23+00:00 21a7f44fd0765fcc5194130b28767786eba1d1e7 Pull devicetree updates from Rob Herring: - A bunch of improvements in dt-check-style. Fix various bindings based on these additional checks. - Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade, hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs, mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and ti,omap-ocp2scp to DT schema format - Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus, HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC - Various binding updates to fix schema warnings in .dts files - Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and regulator, and mailbox.txt - Remove the unused of_overlay_remove_all() function - Fixes for of_check_msi_parent() - Add "i2c-parent" tracking to fw_devlink * tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits) dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller dt-bindings: iommu: Describe MT8195 infra IRQs dt-bindings: clock: mediatek: Add MT8516 fallbacks dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY of: overlay: remove unused of_overlay_remove_all() dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema dt-bindings: bus: Add HiSilicon local bus dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC dt-bindings: vendor-prefixes: add Ambarella dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema of/irq: Stop the MSI walk at the first msi-parent of/irq: Fix device node refcount leak in of_check_msi_parent() dt-bindings: display: faraday,tve200: Use a level-high interrupt ... 
Pull devicetree updates from Rob Herring:

 - A bunch of improvements in dt-check-style. Fix various bindings based
   on these additional checks.

 - Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade,
   hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs,
   mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and
   ti,omap-ocp2scp to DT schema format

 - Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO
   PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus,
   HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC

 - Various binding updates to fix schema warnings in .dts files

 - Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and
   regulator, and mailbox.txt

 - Remove the unused of_overlay_remove_all() function

 - Fixes for of_check_msi_parent()

 - Add "i2c-parent" tracking to fw_devlink

* tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits)
  dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller
  dt-bindings: iommu: Describe MT8195 infra IRQs
  dt-bindings: clock: mediatek: Add MT8516 fallbacks
  dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema
  dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema
  dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema
  dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY
  of: overlay: remove unused of_overlay_remove_all()
  dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema
  dt-bindings: bus: Add HiSilicon local bus
  dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu
  dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC
  dt-bindings: vendor-prefixes: add Ambarella
  dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings
  dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints
  dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema
  dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema
  of/irq: Stop the MSI walk at the first msi-parent
  of/irq: Fix device node refcount leak in of_check_msi_parent()
  dt-bindings: display: faraday,tve200: Use a level-high interrupt
  ...
Merge tag 'media/v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media 2026-10-25T05:27:32+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-10-25T05:27:32+00:00 42e6549eafc66f3648319585680ba0c71c2461da Pull media updates from Mauro Carvalho Chehab: - v4l2 core: - improve subdev and pixformat kAPI; - fix P010 format info and add Y12 format info; - add fwnode_graph_for_each_endpoint_scoped(); - New sensor drivers: - Sony IMX576 - OmniVision OS02G10, OV05C10 and OG0VA1B - Samsung S5KJN5 - Himax HM1246 - Maxim GMSL2/3: add support for MAX9296A, MAX96717, and MAX96724 - Intel IPU6: add support for IPU7, IPU7.5 and IPU8 - NXP: add support for i.MX95 CSI pixel formatter driver - ITE: add driver for IT6625/IT6626 HDMI bridge - Qualcomm: add CSI2 3ph DPHY driver - Rockchip: add rk3576 MIPI capture vicap driver - STM32 DCMIPP: Add STM32MP25 subdevices - Lots of driver fixes and cleanups * tag 'media/v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (596 commits) media: i2c: imx576: Fix line length register media: ov05c10: Remove duplicated writes to analogue gain register media: ov05c10: Power management fixes media: ov05c10: Set reset GPIO high when acquiring it media: ov05c10: Small cleanups media: maxim-serdes: Disable test pattern generator for now media: mc: Keep INTERNAL pad flags just for the kernel, for now media: i2c: imx576: select VIDEO_CCS_PLL to repair build error media: Documentation: mc: Fix Stream reference media: i2c: add imx576 image sensor driver dt-bindings: media: i2c: Add imx576 sensor media: i2c: maxim-serdes: add MAX9296A driver media: i2c: remove MAX96714 driver media: i2c: maxim-serdes: add MAX96724 driver staging: media: remove MAX96712 driver arm64: defconfig: disable deprecated MAX96712 driver media: i2c: maxim-serdes: add MAX96717 driver media: i2c: remove MAX96717 driver media: i2c: add Maxim GMSL2/3 deserializer framework media: i2c: add Maxim GMSL2/3 serializer framework ... 
Pull media updates from Mauro Carvalho Chehab:

 - v4l2 core:
     - improve subdev and pixformat kAPI;
     - fix P010 format info and add Y12 format info;
     - add fwnode_graph_for_each_endpoint_scoped();

 - New sensor drivers:
     - Sony IMX576
     - OmniVision OS02G10, OV05C10 and OG0VA1B
     - Samsung S5KJN5
     - Himax HM1246

 - Maxim GMSL2/3: add support for MAX9296A, MAX96717, and MAX96724

 - Intel IPU6: add support for IPU7, IPU7.5 and IPU8

 - NXP: add support for i.MX95 CSI pixel formatter driver

 - ITE: add driver for IT6625/IT6626 HDMI bridge

 - Qualcomm: add CSI2 3ph DPHY driver

 - Rockchip: add rk3576 MIPI capture vicap driver

 - STM32 DCMIPP: Add STM32MP25 subdevices

 - Lots of driver fixes and cleanups

* tag 'media/v7.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (596 commits)
  media: i2c: imx576: Fix line length register
  media: ov05c10: Remove duplicated writes to analogue gain register
  media: ov05c10: Power management fixes
  media: ov05c10: Set reset GPIO high when acquiring it
  media: ov05c10: Small cleanups
  media: maxim-serdes: Disable test pattern generator for now
  media: mc: Keep INTERNAL pad flags just for the kernel, for now
  media: i2c: imx576: select VIDEO_CCS_PLL to repair build error
  media: Documentation: mc: Fix Stream reference
  media: i2c: add imx576 image sensor driver
  dt-bindings: media: i2c: Add imx576 sensor
  media: i2c: maxim-serdes: add MAX9296A driver
  media: i2c: remove MAX96714 driver
  media: i2c: maxim-serdes: add MAX96724 driver
  staging: media: remove MAX96712 driver
  arm64: defconfig: disable deprecated MAX96712 driver
  media: i2c: maxim-serdes: add MAX96717 driver
  media: i2c: remove MAX96717 driver
  media: i2c: add Maxim GMSL2/3 deserializer framework
  media: i2c: add Maxim GMSL2/3 serializer framework
  ...