linux-toradex.git/Documentation/devicetree/bindings/dma/xilinx, branch master

dt-bindings: dma: xilinx: Fix "xlnx,irq-delay" type

2026-07-01T09:08:20+00:00

"xlnx,irq-delay" programs an 8-bit delay field in the DMA control
register, and the driver stores and reads it as a byte. The binding
described the property as a uint32 cell, which made the helper type
check report the driver as wrong.

Document "xlnx,irq-delay" as uint8 so the generated schema reflects
the hardware field width and the existing driver access.

Assisted-by: Codex:gpt-5-5
Signed-off-by: Rob Herring (Arm) 
Reviewed-by: Radhey Shyam Pandey 
Link: https://patch.msgid.link/20260612215226.1887726-1-robh@kernel.org
Signed-off-by: Vinod Koul

dt-bindings: dma: xlnx,axi-dma: Restore xlnx,flush-fsync as u32

2026-07-01T09:03:33+00:00

The DT schema conversion incorrectly changed xlnx,flush-fsync from a u32
property to a boolean. The original binding documented values 1, 2, and 3
to select which VDMA channel(s) flush on frame sync.
Restore the uint32 type with the documented enum values and fix the
example accordingly.

Fixes: 2d5c2952b972 ("dt-bindings: dma: xlnx,axi-dma: Convert to DT schema")
Signed-off-by: Suraj Gupta 
Acked-by: Conor Dooley 
Link: https://patch.msgid.link/20260625161016.1249570-1-suraj.gupta2@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dma: xlnx,axi-dma: Convert to DT schema

2026-03-17T10:56:24+00:00

Convert the bindings document for Xilinx DMA.
No changes to existing binding description.

Signed-off-by: Abin Joseph 
Reviewed-by: Rob Herring (Arm) 
Link: https://patch.msgid.link/20260309033444.3472359-1-abin.joseph@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dma: xilinx: Simplify dma-coherent property

2025-11-21T12:15:04+00:00

Common boolean properties need to be only allowed in the binding
(":true"), because their type is already defined by core DT schema.
Simplify dma-coherent property to match common syntax.

Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Harini Katakam 
Link: https://patch.msgid.link/20251115122120.35315-5-krzk@kernel.org
Signed-off-by: Vinod Koul

dt-bindings: dmaengine: xilinx_dma: Remove DMA client properties

2025-09-02T07:06:35+00:00

Remove DMA client section mentioned in the dt-bindings as it is
not required to document client bindings in dmaengine bindings.

Signed-off-by: Abin Joseph 
Signed-off-by: Radhey Shyam Pandey 
Acked-by: Rob Herring 
Signed-off-by: Abin Joseph 
Link: https://lore.kernel.org/r/20250825130423.5739-1-abin.joseph@amd.com
Signed-off-by: Vinod Koul

dt-bindings: xilinx: Deprecate header with firmware constants

2025-02-21T06:58:35+00:00

Firmware contants do not fit the purpose of bindings because they are not
independent IDs for abstractions. They are more or less just contants which
better to wire via header with DT which is using it.
That's why add deprecated message to dt binding header and also update
existing dt bindings not to use macros from the header  and replace them by
it's value. Actually value is not relevant because it is only example.

The similar changes have been done by commit 9d9292576810 ("dt-bindings:
pinctrl: samsung: deprecate header with register constants").

Acked-by: Jonathan Cameron 
Acked-by: Vinod Koul 
Acked-by: Conor Dooley 
Signed-off-by: Michal Simek 
Link: https://lore.kernel.org/r/2a6f0229522327939e6893565e540b75f854a37b.1738600745.git.michal.simek@amd.com

dt-bindings: dmaengine: zynqmp_dma: Add a new compatible string

2024-08-29T17:16:16+00:00

Add compatible string "amd,versal2-dma-1.0" to support AMD Versal Gen 2
platform.

AMD Versal Gen 2 has 8 LPD DMA IPs in PS that can be used as general
purpose DMAs which is designed to support memory to memory and memory to
IO buffer transfer. Versal Gen 2 DMA IP has different interrupt register
offset.

Signed-off-by: Abin Joseph 
Acked-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20240808100024.317497-2-abin.joseph@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dmaengine: zynqmp_dma: add xlnx,bus-width required property

2023-09-28T11:22:40+00:00

xlnx,bus-width is a required property. In yaml conversion somehow
it got missed out. Bring it back and mention it in required list.
Also add Harini and myself to the maintainer list.

Fixes: 5a04982df8da ("dt-bindings: dmaengine: zynqmp_dma: convert to yaml")
Signed-off-by: Radhey Shyam Pandey 
Acked-by: Krzysztof Kozlowski 
Reviewed-by: Michael Tretter 
Reviewed-by: Peter Korsgaard 
Link: https://lore.kernel.org/r/1695216326-3841352-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property

2023-08-21T13:10:36+00:00

Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
timeout value and causes the DMA engine to generate an interrupt after the
delay time period has expired. Timer begins counting at the end of a packet
and resets with receipt of a new packet or a timeout event occurs.

This property is useful when AXI DMA is connected to the streaming IP i.e
axiethernet where inter packet latency is critical while still taking the
benefit of interrupt coalescing.

Signed-off-by: Radhey Shyam Pandey 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/1691387509-2113129-3-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul

dt-bindings: dmaengine: xilinx_dma:Add xlnx,axistream-connected property

2023-08-21T13:10:36+00:00

Add an optional AXI DMA property 'xlnx,axistream-connected'. This
can be specified to indicate that DMA is connected to a streaming IP
in the hardware design and dma driver needs to do some additional
handling i.e pass metadata and perform streaming IP specific
configuration.

Signed-off-by: Radhey Shyam Pandey 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/1691387509-2113129-2-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Vinod Koul