linux-toradex.git/Documentation/devicetree/bindings/dma, branch master Linux kernel for Apalis and Colibri modules Merge tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine 2026-02-17T19:47:17+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-02-17T19:47:17+00:00 e81dd54f62c753dd423d1a9b62481a1c599fb975 Pull dmaengine updates from Vinod Koul: "Core: - Add Frank Li as susbstem reviewer to help with reviews New Support: - Mediatek support for Dimensity 6300 and 9200 controller - Qualcomm Kaanapali and Glymur GPI DMA engine - Synopsis DW AXI Agilex5 - Renesas RZ/V2N SoC - Atmel microchip lan9691-dma - Tegra ADMA tegra264 Updates: - sg_nents_for_dma() helper use in subsystem - pm_runtime_mark_last_busy() redundant call update for subsystem - Residue support for xilinx AXIDMA driver - Intel Max SGL Size Support and capabilities for DSA3.0 - AXI dma larger than 32bits address support" * tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (64 commits) dmaengine: add Frank Li as reviewer dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16 dmaengine: fsl-edma: don't explicitly disable clocks in .remove() dmaengine: xilinx: xdma: use sg_nents_for_dma() helper dmaengine: sh: use sg_nents_for_dma() helper dmaengine: sa11x0: use sg_nents_for_dma() helper dmaengine: qcom: bam_dma: use sg_nents_for_dma() helper dmaengine: qcom: adm: use sg_nents_for_dma() helper dmaengine: pxa-dma: use sg_nents_for_dma() helper dmaengine: lgm: use sg_nents_for_dma() helper dmaengine: k3dma: use sg_nents_for_dma() helper dmaengine: dw-axi-dmac: use sg_nents_for_dma() helper dmaengine: bcm2835-dma: use sg_nents_for_dma() helper dmaengine: axi-dmac: use sg_nents_for_dma() helper dmaengine: altera-msgdma: use sg_nents_for_dma() helper scatterlist: introduce sg_nents_for_dma() helper dmaengine: idxd: Add Max SGL Size Support for DSA3.0 dmaengine: idxd: Expose DSA3.0 capabilities through sysfs dmaengine: sh: rz-dmac: Make channel irq local dmaengine: pl08x: Fix comment stating the difference between PL080 and PL081 ... 
Pull dmaengine updates from Vinod Koul:
 "Core:
   - Add Frank Li as susbstem reviewer to help with reviews

  New Support:
   - Mediatek support for Dimensity 6300 and 9200 controller
   - Qualcomm Kaanapali and Glymur GPI DMA engine
   - Synopsis DW AXI Agilex5
   - Renesas RZ/V2N SoC
   - Atmel microchip lan9691-dma
   - Tegra ADMA tegra264

  Updates:
   - sg_nents_for_dma() helper use in subsystem
   - pm_runtime_mark_last_busy() redundant call update for subsystem
   - Residue support for xilinx AXIDMA driver
   - Intel Max SGL Size Support and capabilities for DSA3.0
   - AXI dma larger than 32bits address support"

* tag 'dmaengine-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (64 commits)
  dmaengine: add Frank Li as reviewer
  dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16
  dmaengine: fsl-edma: don't explicitly disable clocks in .remove()
  dmaengine: xilinx: xdma: use sg_nents_for_dma() helper
  dmaengine: sh: use sg_nents_for_dma() helper
  dmaengine: sa11x0: use sg_nents_for_dma() helper
  dmaengine: qcom: bam_dma: use sg_nents_for_dma() helper
  dmaengine: qcom: adm: use sg_nents_for_dma() helper
  dmaengine: pxa-dma: use sg_nents_for_dma() helper
  dmaengine: lgm: use sg_nents_for_dma() helper
  dmaengine: k3dma: use sg_nents_for_dma() helper
  dmaengine: dw-axi-dmac: use sg_nents_for_dma() helper
  dmaengine: bcm2835-dma: use sg_nents_for_dma() helper
  dmaengine: axi-dmac: use sg_nents_for_dma() helper
  dmaengine: altera-msgdma: use sg_nents_for_dma() helper
  scatterlist: introduce sg_nents_for_dma() helper
  dmaengine: idxd: Add Max SGL Size Support for DSA3.0
  dmaengine: idxd: Expose DSA3.0 capabilities through sysfs
  dmaengine: sh: rz-dmac: Make channel irq local
  dmaengine: pl08x: Fix comment stating the difference between PL080 and PL081
  ...
dt-bindings: dma: qcom,gpi: Update max interrupts lines to 16 2026-02-04T16:58:38+00:00 Pankaj Patil pankaj.patil@oss.qualcomm.com 2025-12-31T13:31:14+00:00 876cbb60227fcfbcfcabf458eee5bc52cf5fbac0 Update interrupt maxItems to 16 from 13 per GPI instance to support Glymur, Qualcomm's latest gen SoC Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251231133114.2752822-1-pankaj.patil@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Update interrupt maxItems to 16 from 13 per GPI instance to support
Glymur, Qualcomm's latest gen SoC

Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251231133114.2752822-1-pankaj.patil@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Merge tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt 2026-01-28T15:56:11+00:00 Arnd Bergmann arnd@arndb.de 2026-01-28T15:56:11+00:00 1daa947cb29e4d48999daefd4dd0e06531d1f92f dt-bindings: Changes for v6.20-rc1 This series updates various DT bindings for Tegra architecture, primarily focusing on schema validation fixes and new feature documentation for Tegra234 and Tegra264 SoCs. Key changes include converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock support). Additionally, it resolves legacy warnings for Tegra30/132 display and VI interfaces. * tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: display: tegra: document Tegra30 VI and VIP dt-bindings: display: tegra: document Tegra132 MIPI calibration device dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema dt-bindings: dma: Update ADMA bindings for tegra264 dt-bindings: iommu: Add NVIDIA Tegra CMDQV support dt-bindings: memory: tegra: Document DBB clock for Tegra264 dt-bindings: tegra: pmc: Update aotag as an optional aperture 
dt-bindings: Changes for v6.20-rc1

This series updates various DT bindings for Tegra architecture,
primarily focusing on schema validation fixes and new feature
documentation for Tegra234 and Tegra264 SoCs. Key changes include
converting Tegra20 NAND bindings to YAML, and updating memory, DMA, and
IOMMU definitions for Tegra264 (introducing CMDQV and DBB clock
support). Additionally, it resolves legacy warnings for Tegra30/132
display and VI interfaces.

* tag 'tegra-for-6.20-dt-bindings-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: display: tegra: document Tegra30 VI and VIP
  dt-bindings: display: tegra: document Tegra132 MIPI calibration device
  dt-bindings: mtd: nvidia,tegra20-nand: convert to DT schema
  dt-bindings: dma: Update ADMA bindings for tegra264
  dt-bindings: iommu: Add NVIDIA Tegra CMDQV support
  dt-bindings: memory: tegra: Document DBB clock for Tegra264
  dt-bindings: tegra: pmc: Update aotag as an optional aperture
dt-bindings: dma: Update ADMA bindings for tegra264 2026-01-16T18:59:00+00:00 sheetal sheetal@nvidia.com 2025-09-29T10:59:27+00:00 919f6cd469c605f1de2269d46d04ebf80a1af568 - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
- Update ADMA device tree bindings for tegra264 to support up to 64
  interrupt channels by setting 'interrupts' property maxItems to 64.
- Also, update the 'allOf' conditional schema to ensure correct maxItems
  for 'interrupts' based on compatible string, including tegra210 (22)
  and tegra186 (32) ADMA controllers.

Signed-off-by: sheetal <sheetal@nvidia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
dt-bindings: dma: atmel: add microchip,lan9691-dma 2026-01-01T11:41:13+00:00 Robert Marko robert.marko@sartura.hr 2025-12-29T18:37:50+00:00 c47422f4d0a26b25ff59709921eaaf8f916eec7d Document Microchip LAN969x DMA compatible which is compatible to SAMA7G5. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251229184004.571837-10-robert.marko@sartura.hr Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document Microchip LAN969x DMA compatible which is compatible to SAMA7G5.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251229184004.571837-10-robert.marko@sartura.hr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: dma: snps,dw-axi-dmac: Add compatible string for Agilex5 2026-01-01T11:39:48+00:00 Khairul Anuar Romli khairul.anuar.romli@altera.com 2025-12-29T03:49:01+00:00 0a6946644f0d1151d31212820497e1a49fe1a0a6 The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this will cause address truncation and translation faults. Hence introducing "altr,agilex5-axi-dma" to enable platform specific configuration to configure the dma addressable bit mask. Add a fallback capability for the compatible property to allow driver to probe and initialize with a newly added compatible string without requiring additional entry in the driver. Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/dbc775f114445c06c6e4ce424333e1f3cbb92583.1766966955.git.khairul.anuar.romli@altera.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The address bus on Agilex5 is limited to 40 bits. When SMMU is enable this
will cause address truncation and translation faults. Hence introducing
"altr,agilex5-axi-dma" to enable platform specific configuration to
configure the dma addressable bit mask.

Add a fallback capability for the compatible property to allow driver to
probe and initialize with a newly added compatible string without requiring
additional entry in the driver.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/dbc775f114445c06c6e4ce424333e1f3cbb92583.1766966955.git.khairul.anuar.romli@altera.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: dma: pl08x: Do not use plural form of a proper noun PrimeCell 2026-01-01T11:39:07+00:00 Vladimir Zapolskiy vz@mleia.com 2025-12-25T18:15:19+00:00 99e0728b38da1ee343bd3b57bda72c404c693c45 As a proper noun PrimeCell is a single entity and it can not have a plural form, fix the typo. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20251225181519.1401953-1-vz@mleia.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
As a proper noun PrimeCell is a single entity and it can not have a plural
form, fix the typo.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251225181519.1401953-1-vz@mleia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: dma: Update ADMA bindings for tegra264 2025-12-23T11:15:36+00:00 sheetal sheetal@nvidia.com 2025-09-29T10:59:27+00:00 0b4f3aeee766fd3cc3bf254a26b9761d9b53818b - Update ADMA device tree bindings for tegra264 to support up to 64 interrupt channels by setting 'interrupts' property maxItems to 64. - Also, update the 'allOf' conditional schema to ensure correct maxItems for 'interrupts' based on compatible string, including tegra210 (22) and tegra186 (32) ADMA controllers. Signed-off-by: sheetal <sheetal@nvidia.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://patch.msgid.link/20250929105930.1767294-2-sheetal@nvidia.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
- Update ADMA device tree bindings for tegra264 to support up to 64
  interrupt channels by setting 'interrupts' property maxItems to 64.
- Also, update the 'allOf' conditional schema to ensure correct maxItems
  for 'interrupts' based on compatible string, including tegra210 (22)
  and tegra186 (32) ADMA controllers.

Signed-off-by: sheetal <sheetal@nvidia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://patch.msgid.link/20250929105930.1767294-2-sheetal@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Kaanapali and Glymur SoCs 2025-12-23T11:01:54+00:00 Jyothi Kumar Seerapu jyothi.seerapu@oss.qualcomm.com 2025-11-06T03:00:42+00:00 b729eed5b74eeda36d51d6499f1a06ecc974f31a Document the GPI DMA engine on the Kaanapali and Glymur platforms. Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com> Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://patch.msgid.link/20251105-knp-bus-v2-1-ed3095c7013a@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the GPI DMA engine on the Kaanapali and Glymur platforms.

Signed-off-by: Jyothi Kumar Seerapu <jyothi.seerapu@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20251105-knp-bus-v2-1-ed3095c7013a@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: dma: mediatek,uart-dma: Support all SoC generations 2025-12-23T11:01:24+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com 2025-11-13T12:22:24+00:00 fd7843f0da58b37072c1dafa779d128bb36912bf Add support for the APDMA IP found in all of the SoC generations that are currently supported upstream; this includes: - MT8173, MT8183, fully compatible with MT6577 (32-bits) - MT7988, MT8186, MT8188, MT8192, MT8195 and MT6835 (34-bits) - MT6991, MT8196 and MT6985 (35-bits) ...where: - MT6835 is the first SoC where the AP_DMA IP supports 34-bits addressing; and - MT6985 is the first SoC where the AP_DMA IP supports 35-bits addressing. While at it, also add myself in the maintainers list. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20251113122229.23998-4-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add support for the APDMA IP found in all of the SoC generations
that are currently supported upstream; this includes:
 - MT8173, MT8183, fully compatible with MT6577 (32-bits)
 - MT7988, MT8186, MT8188, MT8192, MT8195 and MT6835 (34-bits)
 - MT6991, MT8196 and MT6985 (35-bits)

...where:
 - MT6835 is the first SoC where the AP_DMA IP supports 34-bits
   addressing; and
 - MT6985 is the first SoC where the AP_DMA IP supports 35-bits
   addressing.

While at it, also add myself in the maintainers list.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20251113122229.23998-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>