linux-toradex.git/Documentation/devicetree/bindings/dma, branch v4.10 Linux kernel for Apalis and Colibri modules Merge branch 'topic/st_fdma' into for-linus 2016-12-14T03:37:07+00:00 Vinod Koul vinod.koul@intel.com 2016-12-14T03:37:07+00:00 4625d2a513d60ca9c3e8cae42c8f3d9efc1b4211 






Merge branch 'topic/qcom' into for-linus
2016-12-14T03:36:54+00:00

Vinod Koul
vinod.koul@intel.com

2016-12-14T03:36:54+00:00

90644ad7f2c0292b1a2a98d733bd17f449bb9885












dmaengine: DW DMAC: add multi-block property to device tree
2016-11-30T03:27:50+00:00

Eugeniy Paltsev
Eugeniy.Paltsev@synopsys.com

2016-11-25T14:59:07+00:00

bd2c6636cc59c4626a04d9918953a107f88eaff9

Several versions of DW DMAC have multi block transfers hardware
support. Hardware support of multi block transfers is disabled
by default if we use DT to configure DMAC and software emulation
of multi block transfers used instead.
Add multi-block property, so it is possible to enable hardware
multi block transfers (if present) via DT.

Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.

Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Several versions of DW DMAC have multi block transfers hardware
support. Hardware support of multi block transfers is disabled
by default if we use DT to configure DMAC and software emulation
of multi block transfers used instead.
Add multi-block property, so it is possible to enable hardware
multi block transfers (if present) via DT.

Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.

Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







dmaengine: rcar-dmac: Document R-Car M3-W bindings
2016-11-25T06:25:09+00:00

Ulrich Hecht
ulrich.hecht+renesas@gmail.com

2016-11-24T14:23:06+00:00

942ba9dc133d82e4ce8cb006e7111aa1b3dcaec7

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







dmaengine: nbpfaxi: add optional max-burst property for memory reads/writes
2016-11-14T04:37:58+00:00

Niklas Cassel
niklas.cassel@axis.com

2016-10-24T13:29:15+00:00

9a1a34f3c8612864f18a71febc134957a03eca64

Due to a hardware bug, reading memory (from the Accelerator Coherency Port)
with a burst size equal to the maximum burst size allowed by the DMA
hardware's buffer size will cause a hardware hang on the ARTPEC-6 SoC,
where the only solution is a manual power cycle.
On ARTPEC-6, this hardware bug does not trigger when writing memory (to the
Accelerator Coherency Port) with a burst size equal to the maximum burst
size allowed by the DMA hardware's buffer size.

To avoid this hardware hang, introduce a new optional max-burst property
for memory reads. For completeness, also introduce a max-burst property for
memory writes.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Due to a hardware bug, reading memory (from the Accelerator Coherency Port)
with a burst size equal to the maximum burst size allowed by the DMA
hardware's buffer size will cause a hardware hang on the ARTPEC-6 SoC,
where the only solution is a manual power cycle.
On ARTPEC-6, this hardware bug does not trigger when writing memory (to the
Accelerator Coherency Port) with a burst size equal to the maximum burst
size allowed by the DMA hardware's buffer size.

To avoid this hardware hang, introduce a new optional max-burst property
for memory reads. For completeness, also introduce a max-burst property for
memory writes.

Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







Documentation: DT: qcom_hidma: correct spelling mistakes
2016-10-19T13:32:58+00:00

Sinan Kaya
okaya@codeaurora.org

2016-10-07T05:25:07+00:00

13af1c8c1608e8944b5197264b7c24b7d760e414

Fix the spelling mistakes and extra and statements in the sentences.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Fix the spelling mistakes and extra and statements in the sentences.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







Documentation: DT: qcom_hidma: update binding for MSI
2016-10-19T13:32:58+00:00

Sinan Kaya
okaya@codeaurora.org

2016-10-07T05:25:06+00:00

ef6661bfdf1b34f86c946fcff127cb67d6d6cfb7

Adding a new binding for qcom,hidma-1.1 to distinguish HW supporting
MSI interrupts from the older revision.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Adding a new binding for qcom,hidma-1.1 to distinguish HW supporting
MSI interrupts from the older revision.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







dmaengine: st_fdma: Add STMicroelectronics FDMA DT binding documentation
2016-10-18T14:42:05+00:00

Peter Griffin
peter.griffin@linaro.org

2016-10-18T09:39:09+00:00

897f419add4eae4b55afe8d6248653bb086f1af2

This patch adds the DT binding documentation for the FDMA constroller
found on STi based chipsets from STMicroelectronics.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





This patch adds the DT binding documentation for the FDMA constroller
found on STi based chipsets from STMicroelectronics.

Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>







Merge branch 'topic/imx' into for-linus
2016-10-03T03:47:52+00:00

Vinod Koul
vinod.koul@intel.com

2016-10-03T03:47:52+00:00

ddfaadfa7f4378fe15237086793f6aed5cbff9a3












DT: dmaengine: rcar-dmac: document R8A7743/5 support
2016-09-30T17:58:48+00:00

Sergei Shtylyov
sergei.shtylyov@cogentembedded.com

2016-09-28T22:25:48+00:00

3770f2a6bfe00869a4b83ee3cced0361ab33289a

Renesas  RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>





Renesas  RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
Document RZ/G1[ME] (also known as R8A774[35]) SoC bindings.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>