linux-toradex.git/Documentation/devicetree/bindings/interrupt-controller, branch master Linux kernel for Apalis and Colibri modules dt-bindings: interrupt-controller: econet: Add CPU interrupt mapping 2026-05-11T13:29:30+00:00 Caleb James DeLisle cjd@cjdns.fr 2026-04-30T16:41:56+00:00 02bea6ff684b62c14d5c6eafaee752d24fe62352 In MIPS VEIC mode (Vectored External Interrupt Controller), the hardware stops directly dispatching CPU interrupts such as IPIs or CPU performance counters, and instead it communicates them to the external interrupt controller (the hardware described here) which prioritizes, renumbers, and integrates them with its own hardware interrupt pins. Interrupts from the external controller are then dispatched through a different method via a dispatch table. In effect, the external controller subsumes the CPU controller and becomes the root. 34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136 Since there are interrupts which ought to be controlled by the CPU controller driver - particularly the IPI interrupts - we create a reverse mapping where those interrupts may be sent back to the CPU intc when they are received. This maintains the fiction that there is still a hierarchy, and keeps the DT the same no matter whether the processor is in VEIC mode or not. The econet,cpu-interrupt-map is optional and if omitted, it's assumed that no interrupts need to be mapped. Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr 
In MIPS VEIC mode (Vectored External Interrupt Controller), the
hardware stops directly dispatching CPU interrupts such as IPIs or CPU
performance counters, and instead it communicates them to the external
interrupt controller (the hardware described here) which prioritizes,
renumbers, and integrates them with its own hardware interrupt pins.
Interrupts from the external controller are then dispatched through a
different method via a dispatch table. In effect, the external
controller subsumes the CPU controller and becomes the root.

34K Manual (MD00534) Section 6.3.1.3 rev 1.13 page 136

Since there are interrupts which ought to be controlled by the CPU
controller driver - particularly the IPI interrupts - we create a
reverse mapping where those interrupts may be sent back to the CPU
intc when they are received. This maintains the fiction that there is
still a hierarchy, and keeps the DT the same no matter whether the
processor is in VEIC mode or not. The econet,cpu-interrupt-map is
optional and if omitted, it's assumed that no interrupts need to be
mapped.

Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260430164157.6026-2-cjd@cjdns.fr
dt-bindings: interrupt-controller: Add support for Amlogic A9 SoCs 2026-05-11T13:11:29+00:00 Xianwei Zhao xianwei.zhao@amlogic.com 2026-05-08T07:36:55+00:00 f51c99a0e502dcfd3a1972554ed3f09970a55a07 Update dt-binding document for GPIO interrupt controller of Amlogic A9 SoCs. Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com 
Update dt-binding document for GPIO interrupt controller
of Amlogic A9 SoCs.

Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260508-a9-gpio-irqchip-v1-2-9dc5f3e022e0@amlogic.com
dt-bindings: interrupt-controller: Repurpose binding for unreleased jh8100 for jhb100 2026-04-30T10:53:04+00:00 Changhuang Liang changhuang.liang@starfivetech.com 2026-04-16T06:47:47+00:00 a540d544db1c37d4c138b67384f235a85f79f060 The StarFive JH8100 SoC was discontinued before production. The newly taped-out JHB100 SoC uses the same interrupt controller IP. Rename the binding file, compatible string, and MAINTAINERS entry from "jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated by users, but they exist in the hardware. Mark them as optional. Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com 
The StarFive JH8100 SoC was discontinued before production. The newly
taped-out JHB100 SoC uses the same interrupt controller IP.

Rename the binding file, compatible string, and MAINTAINERS entry from
"jh8100" to "jhb100". In JHB100 SoC, The clocks and resets are not operated
by users, but they exist in the hardware. Mark them as optional.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260416064751.632138-2-changhuang.liang@starfivetech.com
dt-bindings: interrupt-controller: Describe AST2700-A2 hardware instead of A0 2026-04-30T10:53:03+00:00 Ryan Chen ryan_chen@aspeedtech.com 2026-04-07T03:08:04+00:00 51561ad8c89cfdd90314ce78c63553632d95bfd2 Introduce a new binding describing the AST2700 interrupt controller architecture implemented in the A2 production silicon. The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2) prior to mass production. The interrupt architecture was substantially reworked after the A0 revision for A1, and the A1 design is retained unchanged in the A2 production silicon. The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic") was written against the pre-production A0 design. That binding does not accurately describe the interrupt hierarchy and routing model present in A1/A2, where interrupts can be routed to multiple processor-local interrupt controllers (Primary Service Processor (PSP) GIC, Secondary Service Processor (SSP)/Tertiary Service Processor (TSP) NVICs, and BootMCU APLIC) depending on the execution context. Remove the binding for the pre-production A0 design in favour of the binding for the A2 production design. There is no significant user impact from the removal as there are no existing devicetrees in any of Linux, u-boot or Zephyr that make use of the A0 binding. Hardware connectivity between interrupt controllers is expressed using the aspeed,interrupt-ranges property. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Thomas Gleixner <tglx@kernel.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260407-irqchip-v5-1-c0b0a300a057@aspeedtech.com 
Introduce a new binding describing the AST2700 interrupt controller
architecture implemented in the A2 production silicon.

The AST2700 SoC has undergone multiple silicon revisions (A0, A1, A2)
prior to mass production. The interrupt architecture was substantially
reworked after the A0 revision for A1, and the A1 design is retained
unchanged in the A2 production silicon.

The existing AST2700 interrupt controller binding ("aspeed,ast2700-intc-ic")
was written against the pre-production A0 design.

That binding does not accurately describe the interrupt hierarchy and
routing model present in A1/A2, where interrupts can be routed to multiple
processor-local interrupt controllers (Primary Service Processor (PSP) GIC,
Secondary Service Processor (SSP)/Tertiary Service Processor (TSP) NVICs,
and BootMCU APLIC) depending on the execution context.

Remove the binding for the pre-production A0 design in favour of the
binding for the A2 production design. There is no significant user
impact from the removal as there are no existing devicetrees in any
of Linux, u-boot or Zephyr that make use of the A0 binding.

Hardware connectivity between interrupt controllers is expressed using
the aspeed,interrupt-ranges property.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Signed-off-by: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260407-irqchip-v5-1-c0b0a300a057@aspeedtech.com
Merge tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2026-04-17T21:09:02+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-04-17T21:09:02+00:00 e2d10998e4293a27c0389870b5fdf736a71d61ef Pull devicetree updates from Rob Herring: "DT core: - Cleanup of the reserved memory code to keep CMA specifics in CMA code - Add and convert several users to new of_machine_get_match() helper - Validate nul termination in string properties - Update dtc to upstream v1.7.2-69-g53373d135579 - Limit matching reserved memory devices to /reserved-memory nodes - Fix some UAF in unittests - Remove Baikal SoC bus driver - Fix false DT_SPLIT_BINDING_PATCH checkpatch warning - Allow fw_devlink device-tree on x86 - Fix kerneldoc return description for of_property_count_elems_of_size() DT bindings: - Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc, qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem, qcom,hawi-pdc, and lg,sw49410 bindings - Convert arm,vexpress-scc to DT schema - Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores. - Move some dual-link display panels to the dual-link schema - Drop mux controller node name constraints - Remove Baikal SoC bus bindings - Fix a false warning in the thermal trip node binding" * tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits) dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes of: unittest: fix use-after-free in testdrv_probe() of: unittest: fix use-after-free in of_unittest_changeset() dt-bindings: qcom,pdc: document the Hawi Power Domain Controller dt-bindings: ARM: arm,vexpress-scc: convert to DT schema drivers/of: fdt: validate flat DT string properties before string use drivers/of: fdt: validate stdout-path properties before parsing them dt-bindings: sram: Document qcom,hawi-imem compatible dt-bindings: sram: Allow multiple-word prefixes to sram subnode dt-bindings: sram: Document qcom,milos-imem scripts/dtc: Update to upstream version v1.7.2-69-g53373d135579 of: property: Allow fw_devlink device-tree on x86 dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles dt-bindings: display: lt8912b: Drop redundant endpoint properties dt-bindings: opp-v2: Fix example 3 CPU reg value dt-bindings: connector: add pd-disable dependency ... 
Pull devicetree updates from Rob Herring:
 "DT core:

   - Cleanup of the reserved memory code to keep CMA specifics in CMA
     code

   - Add and convert several users to new of_machine_get_match() helper

   - Validate nul termination in string properties

   - Update dtc to upstream v1.7.2-69-g53373d135579

   - Limit matching reserved memory devices to /reserved-memory nodes

   - Fix some UAF in unittests

   - Remove Baikal SoC bus driver

   - Fix false DT_SPLIT_BINDING_PATCH checkpatch warning

   - Allow fw_devlink device-tree on x86

   - Fix kerneldoc return description for of_property_count_elems_of_size()

  DT bindings:

   - Add fsl,imx25-aips, fsl,imx25-tcq, qcom,eliza-pdc,
     qcom,eliza-spmi-pmic-arb, qcom,hawi-imem, qcom,milos-imem,
     qcom,hawi-pdc, and lg,sw49410 bindings

   - Convert arm,vexpress-scc to DT schema

   - Deprecate Qualcomm generic CPU compatibles. Add Apple M3 CPU cores.

   - Move some dual-link display panels to the dual-link schema

   - Drop mux controller node name constraints

   - Remove Baikal SoC bus bindings

   - Fix a false warning in the thermal trip node binding"

* tag 'devicetree-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (39 commits)
  dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible
  dt-bindings: display: ti, am65x-dss: Fix AM62L DSS reg and clock constraints
  dt-bindings: display: simple: Move Innolux G156HCE-L01 panel to dual-link
  dt-bindings: display: simple: Move AUO 21.5" FHD to dual-link
  dt-bindings: thermal: Fix false warning with 'phandle' in trips nodes
  of: unittest: fix use-after-free in testdrv_probe()
  of: unittest: fix use-after-free in of_unittest_changeset()
  dt-bindings: qcom,pdc: document the Hawi Power Domain Controller
  dt-bindings: ARM: arm,vexpress-scc: convert to DT schema
  drivers/of: fdt: validate flat DT string properties before string use
  drivers/of: fdt: validate stdout-path properties before parsing them
  dt-bindings: sram: Document qcom,hawi-imem compatible
  dt-bindings: sram: Allow multiple-word prefixes to sram subnode
  dt-bindings: sram: Document qcom,milos-imem
  scripts/dtc: Update to upstream version v1.7.2-69-g53373d135579
  of: property: Allow fw_devlink device-tree on x86
  dt-bindings: arm: cpus: Add Apple M3 CPU core compatibles
  dt-bindings: display: lt8912b: Drop redundant endpoint properties
  dt-bindings: opp-v2: Fix example 3 CPU reg value
  dt-bindings: connector: add pd-disable dependency
  ...
Merge tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2026-04-17T03:34:34+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-04-17T03:34:34+00:00 31b43c079f9aa55754c20404a42bca9a49e01f60 Pull SoC driver updates from Arnd Bergmann: "The driver updates again are all over the place with many minor fixes going into platform specific code. The most notable changes are: - Support for Microchip pic64gx system controllers - Work on cleaning up devicetree bindings for SoC drivers, and converting them into the new format - Lots of smaller changes for Qualcomm SoC drivers, including support for a number of newly supported chips - reset controller API cleanups and a new driver for Cix Sky1 - Reworks of the Tegra PMC and CBB drivers, along with a change to how individual Tegra SoCs get selected in Kconfig and BPMP firmware driver updates including a refresh of the ABI header to match the version used by firmware - STM32 updates to the firewall bus driver and support for the debug bus through OP-TEE - SCMI firmware driver improvements for reliability, in particular for dealing with broken firmware interrupts - Memory driver updates for Tegra, and a patch to remove the unused Baikal T1 driver" * tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits) firmware: arm_ffa: Use the correct buffer size during RXTX_MAP firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X clk: spear: fix resource leak in clk_register_vco_pll() reset: rzv2h-usb2phy: Add support for VBUS mux controller registration reset: rzv2h-usb2phy: Convert to regmap API dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property soc: microchip: add mpfs gpio interrupt mux driver dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux gpio: mpfs: Add interrupt support soc: qcom: ubwc: add helpers to get programmable values soc: qcom: ubwc: add helper to get min_acc length firmware: qcom: scm: Register gunyah watchdog device soc: qcom: socinfo: Add SoC ID for SA8650P dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P firmware: qcom: scm: Allow QSEECOM on Mahua CRD soc: qcom: wcnss: simplify allocation of req soc: qcom: pd-mapper: Add support for Eliza soc: qcom: aoss: compare against normalized cooling state soc: qcom: llcc: fix v1 SB syndrome register offset ... 
Pull SoC driver updates from Arnd Bergmann:
 "The driver updates again are all over the place with many minor fixes
  going into platform specific code. The most notable changes are:

   - Support for Microchip pic64gx system controllers
   - Work on cleaning up devicetree bindings for SoC drivers, and
     converting them into the new format
   - Lots of smaller changes for Qualcomm SoC drivers, including support
     for a number of newly supported chips
   - reset controller API cleanups and a new driver for Cix Sky1
   - Reworks of the Tegra PMC and CBB drivers, along with a change to
     how individual Tegra SoCs get selected in Kconfig and BPMP firmware
     driver updates including a refresh of the ABI header to match the
     version used by firmware
   - STM32 updates to the firewall bus driver and support for the debug
     bus through OP-TEE
   - SCMI firmware driver improvements for reliability, in particular
     for dealing with broken firmware interrupts
   - Memory driver updates for Tegra, and a patch to remove the unused
     Baikal T1 driver"

* tag 'soc-drivers-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (193 commits)
  firmware: arm_ffa: Use the correct buffer size during RXTX_MAP
  firmware: qcom: scm: Allow QSEECOM on Lenovo IdeaCentre Mini X
  clk: spear: fix resource leak in clk_register_vco_pll()
  reset: rzv2h-usb2phy: Add support for VBUS mux controller registration
  reset: rzv2h-usb2phy: Convert to regmap API
  dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/G3E USB2PHY reset
  dt-bindings: reset: renesas,rzv2h-usb2phy: Add '#mux-state-cells' property
  soc: microchip: add mpfs gpio interrupt mux driver
  dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux
  gpio: mpfs: Add interrupt support
  soc: qcom: ubwc: add helpers to get programmable values
  soc: qcom: ubwc: add helper to get min_acc length
  firmware: qcom: scm: Register gunyah watchdog device
  soc: qcom: socinfo: Add SoC ID for SA8650P
  dt-bindings: arm: qcom,ids: Add SoC ID for SA8650P
  firmware: qcom: scm: Allow QSEECOM on Mahua CRD
  soc: qcom: wcnss: simplify allocation of req
  soc: qcom: pd-mapper: Add support for Eliza
  soc: qcom: aoss: compare against normalized cooling state
  soc: qcom: llcc: fix v1 SB syndrome register offset
  ...
dt-bindings: qcom,pdc: document the Hawi Power Domain Controller 2026-04-15T20:06:12+00:00 Mukesh Ojha mukesh.ojha@oss.qualcomm.com 2026-04-01T12:50:04+00:00 e9cd85a42638090181a2af38684656d1cbc574e5 Document the Power Domain Controller on the Qualcomm Hawi SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com> Link: https://patch.msgid.link/20260401125004.592925-1-mukesh.ojha@oss.qualcomm.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> 
Document the Power Domain Controller on the Qualcomm Hawi SoC.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
Link: https://patch.msgid.link/20260401125004.592925-1-mukesh.ojha@oss.qualcomm.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Merge tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/drivers 2026-04-04T14:09:43+00:00 Krzysztof Kozlowski krzk@kernel.org 2026-04-04T14:09:43+00:00 d7dbdadad2387147fa22c62faa66f3d9d1421ee8 dt-bindings: Changes for v7.1-rc1 This contains a few conversions to DT schema along with various additions and fixes to reduce the amount of validation warnings. Included are also a new binding for the PCIe controller found on Tegra264 as well as compatible strings for the Jetson AGX Thor Developer Kit. * tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit dt-bindings: display: tegra: Document Tegra20 HDMI port dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings dt-bindings: memory: tegra210: Mark EMC as cooling device dt-bindings: memory: Add Tegra210 memory controller bindings dt-bindings: phy: tegra: Document Tegra210 USB PHY dt-bindings: arm: tegra: Add missing compatible strings dt-bindings: interrupt-controller: tegra: Fix reg entries dt-bindings: clock: tegra124-dfll: Convert to json-schema dt-bindings: phy: tegra-xusb: Document Type C support dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> 
dt-bindings: Changes for v7.1-rc1

This contains a few conversions to DT schema along with various
additions and fixes to reduce the amount of validation warnings.

Included are also a new binding for the PCIe controller found on
Tegra264 as well as compatible strings for the Jetson AGX Thor
Developer Kit.

* tag 'tegra-for-7.1-dt-bindings' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  dt-bindings: arm: tegra: Document Jetson AGX Thor DevKit
  dt-bindings: display: tegra: Document Tegra20 HDMI port
  dt-bindings: arm: tegra: Add Tegra238 CBB compatible strings
  dt-bindings: memory: tegra210: Mark EMC as cooling device
  dt-bindings: memory: Add Tegra210 memory controller bindings
  dt-bindings: phy: tegra: Document Tegra210 USB PHY
  dt-bindings: arm: tegra: Add missing compatible strings
  dt-bindings: interrupt-controller: tegra: Fix reg entries
  dt-bindings: clock: tegra124-dfll: Convert to json-schema
  dt-bindings: phy: tegra-xusb: Document Type C support
  dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
dt-bindings: interrupt-controller: tegra: Fix reg entries 2026-03-27T15:25:44+00:00 Thierry Reding treding@nvidia.com 2026-02-23T14:32:59+00:00 cafacd15e84d0b8163f2df92555a265e0b84e236 Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30 which supports only 5 entries. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Tegra210 takes exactly 6 "reg" property entries, as opposed to Tegra30
which supports only 5 entries.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
dt-bindings: interrupt-controller: fsl,irqsteer: add S32N79 support 2026-03-26T16:11:49+00:00 Ciprian Marian Costea ciprianmarian.costea@oss.nxp.com 2026-03-11T08:11:50+00:00 0b7973dfb7467f69843fb56bf62c7cb440a0bc3c Add compatible string for the interrupt steering controller used in NXP S32N79 SoC. The S32N79 SoC differs from the i.MX version by not implementing the CHANCTRL register, but otherwise maintains the same programming model and register layout. Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com> Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Frank Li <Frank.Li@nxp.com> 
Add compatible string for the interrupt steering controller used in NXP
S32N79 SoC.

The S32N79 SoC differs from the i.MX version by not implementing the
CHANCTRL register, but otherwise maintains the same programming model and
register layout.

Co-developed-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>