linux-toradex.git/Documentation/devicetree/bindings/interrupt-controller, branch v6.7-rc1 Linux kernel for Apalis and Colibri modules Merge tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2023-11-02T00:37:04+00:00 Linus Torvalds torvalds@linux-foundation.org 2023-11-02T00:37:04+00:00 c035f0268b87fc21f517f638b3bad26c81babc85 Pull SoC DT updates from Arnd Bergmann: "There are a couple new SoCs that are supported for the first time: - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU cores - Sophgo makes RISC-V based chips, and we now support the CV1800B chip used in the milkv-duo board and the massive sg2042 chip in the milkv-pioneer, a 64-core developer workstation. - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon 7c and gets added with some Xiaomi phones - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC and the RZ/G3S (R9A08G045) embedded SoC. There are also a bunch of newly supported machines that use already supported chips. On the 32-bit side, we have: - USRobotics USR8200 is a NAS/Firewall/router based on the ancient Intel IXP4xx platform - A couple of machines based on the NXP i.MX5 and i.MX6 platforms - One machine each for Allwinner V3s, Aspeed AST2600, Microchip sama5d29 and ST STM32mp157 The other ones all use arm64 cores on chips from allwinner, amlogic, freescale, mediatek, qualcomm and rockchip" * tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits) ARM: dts: BCM5301X: Set switch ports for Linksys EA9200 ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U arm64: dts: socionext: add missing cache properties riscv: dts: thead: convert isa detection to new properties arm64: dts: Update cache properties for socionext arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM arm64: dts: ti: k3-am62p: Add nodes for more IPs arm64: dts: rockchip: Add Turing RK1 SoM support dt-bindings: arm: rockchip: Add Turing RK1 dt-bindings: vendor-prefixes: add turing arm64: dts: rockchip: Add DFI to rk3588s arm64: dts: rockchip: Add DFI to rk356x arm64: dts: rockchip: Always enable DFI on rk3399 ... 
Pull SoC DT updates from Arnd Bergmann:
 "There are a couple new SoCs that are supported for the first time:

   - AMD Pensando Elba is a data processing unit based on Cortex-A72 CPU
     cores

   - Sophgo makes RISC-V based chips, and we now support the CV1800B
     chip used in the milkv-duo board and the massive sg2042 chip in the
     milkv-pioneer, a 64-core developer workstation.

   - Qualcomm Snapdragon 720G (sm7125) is a close relative of Snapdragon
     7c and gets added with some Xiaomi phones

   - Renesas gains support for the R8A779F4 (R-Car S4-8) automotive SoC
     and the RZ/G3S (R9A08G045) embedded SoC.

  There are also a bunch of newly supported machines that use already
  supported chips. On the 32-bit side, we have:

   - USRobotics USR8200 is a NAS/Firewall/router based on the ancient
     Intel IXP4xx platform

   - A couple of machines based on the NXP i.MX5 and i.MX6 platforms

   - One machine each for Allwinner V3s, Aspeed AST2600, Microchip
     sama5d29 and ST STM32mp157

  The other ones all use arm64 cores on chips from allwinner, amlogic,
  freescale, mediatek, qualcomm and rockchip"

* tag 'soc-dt-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (641 commits)
  ARM: dts: BCM5301X: Set switch ports for Linksys EA9200
  ARM: dts: BCM5301X: Set fixed-link for extra Netgear R8000 CPU ports
  ARM: dts: BCM5301X: Explicitly disable unused switch CPU ports
  ARM: dts: BCM5301X: Relicense Vivek's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Relicense Felix's code to the GPL 2.0+ / MIT
  ARM: dts: BCM5301X: Set MAC address for Asus RT-AC87U
  arm64: dts: socionext: add missing cache properties
  riscv: dts: thead: convert isa detection to new properties
  arm64: dts: Update cache properties for socionext
  arm64: dts: ti: k3-am654-idk: Add ICSSG Ethernet ports
  arm64: dts: ti: k3-am654-icssg2: add ICSSG2 Ethernet support
  arm64: dts: ti: k3-am65-main: Add ICSSG IEP nodes
  arm64: dts: ti: k3-am62p5-sk: Updates for SK EVM
  arm64: dts: ti: k3-am62p: Add nodes for more IPs
  arm64: dts: rockchip: Add Turing RK1 SoM support
  dt-bindings: arm: rockchip: Add Turing RK1
  dt-bindings: vendor-prefixes: add turing
  arm64: dts: rockchip: Add DFI to rk3588s
  arm64: dts: rockchip: Add DFI to rk356x
  arm64: dts: rockchip: Always enable DFI on rk3399
  ...
Merge tag 'devicetree-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2023-11-01T04:50:13+00:00 Linus Torvalds torvalds@linux-foundation.org 2023-11-01T04:50:13+00:00 8bc9e6515183935fa0cccaf67455c439afe4982b Pull devicetree updates from Rob Herring: - Add a kselftest to check for unprobed DT devices - Fix address translation for some 3 address cells cases - Refactor firmware node refcounting for AMBA bus - Add bindings for qcom,sm4450-pdc, Qualcomm Kryo 465 CPU, and Freescale QMC HDLC - Add Marantec vendor prefix - Convert qcom,pm8921-keypad, cnxt,cx92755-wdt, da9062-wdt, and atmel,at91rm9200-wdt bindings to DT schema - Several additionalProperties/unevaluatedProperties on child node schemas fixes - Drop reserved-memory bindings which now live in dtschema project - Fix a reference to rockchip,inno-usb2phy.yaml - Remove backlight nodes from display panel examples - Expand example for using DT_SCHEMA_FILES - Merge simple LVDS panel bindings to one binding doc * tag 'devicetree-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (34 commits) dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add support for QMC HDLC dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name dt-bindings: arm,coresight-cti: Add missing additionalProperties on child nodes dt-bindings: arm,coresight-cti: Drop type for 'cpu' property dt-bindings: soundwire: Add reference to soundwire-controller.yaml schema dt-bindings: input: syna,rmi4: Make "additionalProperties: true" explicit media: dt-bindings: ti,ds90ub960: Add missing type for "i2c-alias" dt-bindings: input: qcom,pm8921-keypad: convert to YAML format of: overlay: unittest: overlay_bad_unresolved: Spelling s/ok/okay/ of: address: Consolidate bus .map() functions of: address: Store number of bus flag cells rather than bool of: unittest: Add tests for address translations of: address: Remove duplicated functions of: address: Fix address translation when address-size is greater than 2 dt-bindings: watchdog: cnxt,cx92755-wdt: convert txt to yaml dt-bindings: watchdog: da9062-wdt: convert txt to yaml dt-bindings: watchdog: fsl,scu-wdt: Document imx8dl dt-bindings: watchdog: atmel,at91rm9200-wdt: convert txt to yaml dt-bindings: usb: rockchip,dwc3: update inno usb2 phy binding name ... 
Pull devicetree updates from Rob Herring:

 - Add a kselftest to check for unprobed DT devices

 - Fix address translation for some 3 address cells cases

 - Refactor firmware node refcounting for AMBA bus

 - Add bindings for qcom,sm4450-pdc, Qualcomm Kryo 465 CPU, and
   Freescale QMC HDLC

 - Add Marantec vendor prefix

 - Convert qcom,pm8921-keypad, cnxt,cx92755-wdt, da9062-wdt, and
   atmel,at91rm9200-wdt bindings to DT schema

 - Several additionalProperties/unevaluatedProperties on child node
   schemas fixes

 - Drop reserved-memory bindings which now live in dtschema project

 - Fix a reference to rockchip,inno-usb2phy.yaml

 - Remove backlight nodes from display panel examples

 - Expand example for using DT_SCHEMA_FILES

 - Merge simple LVDS panel bindings to one binding doc

* tag 'devicetree-for-6.7' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (34 commits)
  dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add support for QMC HDLC
  dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Add 'additionalProperties: false' in child nodes
  dt-bindings: soc: fsl: cpm_qe: cpm1-scc-qmc: Fix example property name
  dt-bindings: arm,coresight-cti: Add missing additionalProperties on child nodes
  dt-bindings: arm,coresight-cti: Drop type for 'cpu' property
  dt-bindings: soundwire: Add reference to soundwire-controller.yaml schema
  dt-bindings: input: syna,rmi4: Make "additionalProperties: true" explicit
  media: dt-bindings: ti,ds90ub960: Add missing type for "i2c-alias"
  dt-bindings: input: qcom,pm8921-keypad: convert to YAML format
  of: overlay: unittest: overlay_bad_unresolved: Spelling s/ok/okay/
  of: address: Consolidate bus .map() functions
  of: address: Store number of bus flag cells rather than bool
  of: unittest: Add tests for address translations
  of: address: Remove duplicated functions
  of: address: Fix address translation when address-size is greater than 2
  dt-bindings: watchdog: cnxt,cx92755-wdt: convert txt to yaml
  dt-bindings: watchdog: da9062-wdt: convert txt to yaml
  dt-bindings: watchdog: fsl,scu-wdt: Document imx8dl
  dt-bindings: watchdog: atmel,at91rm9200-wdt: convert txt to yaml
  dt-bindings: usb: rockchip,dwc3: update inno usb2 phy binding name
  ...
dt-bindings: interrupt-controller: Add SOPHGO CV1800B plic 2023-10-07T12:34:05+00:00 Jisheng Zhang jszhang@kernel.org 2023-10-06T12:14:45+00:00 975f0a640ceb41581c4974ed6f368c39478a3bd3 Add compatible string for SOPHGO CV1800B plic. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add compatible string for SOPHGO CV1800B plic.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property 2023-10-07T11:47:12+00:00 Lorenzo Pieralisi lpieralisi@kernel.org 2023-10-06T12:59:25+00:00 5e5c636c69bdba04033161bbb111fbb6f1f6661e The GIC v3 specifications allow redistributors and ITSes interconnect ports used to access memory to be wired up in a way that makes the respective initiators/memory observers non-coherent. Add the standard dma-noncoherent property to the GICv3 bindings to allow firmware to describe the redistributors/ITSes components and interconnect ports behaviour in system designs where the redistributors and ITSes are not coherent with the CPU. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org> Cc: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@kernel.org 
The GIC v3 specifications allow redistributors and ITSes interconnect
ports used to access memory to be wired up in a way that makes the
respective initiators/memory observers non-coherent.

Add the standard dma-noncoherent property to the GICv3 bindings to
allow firmware to describe the redistributors/ITSes components and
interconnect ports behaviour in system designs where the redistributors
and ITSes are not coherent with the CPU.

Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Rob Herring <robh@kernel.org>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231006125929.48591-2-lpieralisi@kernel.org
dt-bindings: interrupt-controller: renesas,irqc: Add r8a779f0 support 2023-10-07T11:47:05+00:00 Geert Uytterhoeven geert+renesas@glider.be 2023-07-27T08:36:23+00:00 977f7c2b275667777cd42ab0e61461617b652b05 Document support for the Interrupt Controller for External Devices (INT-EX) in the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/9467a1c67d5d240211f88336973fa968d39cc860.1690446928.git.geert+renesas@glider.be 
Document support for the Interrupt Controller for External Devices
(INT-EX) in the Renesas R-Car S4-8 (R8A779F0) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/9467a1c67d5d240211f88336973fa968d39cc860.1690446928.git.geert+renesas@glider.be
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document RZ/G2UL SoC 2023-10-07T11:27:39+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2023-10-06T12:10:58+00:00 db712c0089bd8e9e47c286ed772d86fb187d0854 Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC is almost identical to one found on the RZ/G2L SoC the only difference being it can support BUS_ERR_INT for which it has additional registers. Hence new generic compatible string "renesas,r9a07g043u-irqc" is added for RZ/G2UL SoC. Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC interrupt-names property is added so that we can parse them based on names. While at it updated the example node to four spaces and added interrupt-names property. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com 
Document RZ/G2UL (R9A07G043U) IRQC bindings. The IRQC block on RZ/G2UL SoC
is almost identical to one found on the RZ/G2L SoC the only difference
being it can support BUS_ERR_INT for which it has additional registers.
Hence new generic compatible string "renesas,r9a07g043u-irqc" is added
for RZ/G2UL SoC.

Now that we have additional interrupt for RZ/G2UL and RZ/Five SoC
interrupt-names property is added so that we can parse them based on
names.

While at it updated the example node to four spaces and added
interrupt-names property.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20231006121058.13890-1-prabhakar.mahadev-lad.rj@bp.renesas.com
dt-bindings: interrupt-controller: Add Sophgo sg2042 CLINT mswi 2023-10-06T13:40:09+00:00 Inochi Amaoto inochiama@outlook.com 2023-10-04T15:43:47+00:00 942e02e150721413b43068a8073819ad2b7d6314 The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and implements the not yet frozen ACLINT spec. This spec seems to be abandoned, and will not be frozen in the predictable future. Frozen specs required by the RISC-V maintainers before merging content relating to those extensions, therefore a generic compatible is not appropriate. Instead, add new vendor specific compatible strings to identify mswi of sg2042 clint. Signed-off-by: Inochi Amaoto <inochiama@outlook.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> [conor: re-wrote commit message to drop irrelevant sifive,clint discussion] Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
The clint of Sophgo's sg2042 is based off IP designed by T-HEAD, and
implements the not yet frozen ACLINT spec. This spec seems to be
abandoned, and will not be frozen in the predictable future.
Frozen specs required by the RISC-V maintainers before merging content
relating to those extensions, therefore a generic compatible is not
appropriate.
Instead, add new vendor specific compatible strings to identify mswi of
sg2042 clint.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
[conor: re-wrote commit message to drop irrelevant sifive,clint discussion]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: interrupt-controller: Add Sophgo SG2042 PLIC 2023-10-06T13:36:54+00:00 Chen Wang unicorn_wang@outlook.com 2023-10-04T15:42:41+00:00 d975794dddd2ec44f142302c7fd3b86eebec0bee Add compatible string for SOPHGO SG2042 plic. Acked-by: Chao Wei <chao.wei@sophgo.com> Reviewed-by: Guo Ren <guoren@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Chen Wang <unicorn_wang@outlook.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> 
Add compatible string for SOPHGO SG2042 plic.

Acked-by: Chao Wei <chao.wei@sophgo.com>
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
dt-bindings: interrupt-controller: qcom,pdc: document qcom,sm4450-pdc 2023-09-22T20:46:50+00:00 Tengfei Fan quic_tengfan@quicinc.com 2023-09-22T08:10:21+00:00 bc17fd92c1eb7589f1f3df1893e9f62bb35b8cc8 Add SM4450 PDC, which will used in SM4450 DTS. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com> Link: https://lore.kernel.org/r/20230922081026.2799-2-quic_tengfan@quicinc.com Signed-off-by: Rob Herring <robh@kernel.org> 
Add SM4450 PDC, which will used in SM4450 DTS.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20230922081026.2799-2-quic_tengfan@quicinc.com
Signed-off-by: Rob Herring <robh@kernel.org>
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property 2023-09-12T12:40:52+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2022-07-22T15:11:54+00:00 cfa1f9db6d6088118ef311c0927c66072665b47e Update description for '#interrupt-cells' property to utilize the RZG2L_{NMI,IRQX} for the first cell defined in the include/dt-bindings/interrupt-controller/irqc-rzg2l.h file. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Fixes: 96fed779d3d4cb3c ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller") Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20220722151155.21100-3-prabhakar.mahadev-lad.rj@bp.renesas.com 
Update description for '#interrupt-cells' property to utilize the
RZG2L_{NMI,IRQX} for the first cell defined in the
include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fixes: 96fed779d3d4cb3c ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220722151155.21100-3-prabhakar.mahadev-lad.rj@bp.renesas.com