linux-toradex.git/Documentation/devicetree/bindings/iommu, branch master

Merge tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux

2026-06-17T19:24:50+00:00

Pull iommu updates from Joerg Roedel:
 "Core Code:

   - Fix dma-iommu scatterlist length handling in the P2PDMA path

   - Extend the generic IOMMU page-table code with detailed gather
     support for more precise invalidations

   - Add pending-gather tracking to generic page-table invalidation
     handling

   - Add support for smaller virtual address sizes in the generic AMDv1
     page-table format, including KUnit coverage

   - Fix page-size bitmap calculation for smaller VA configurations

   - Rework Arm io-pgtable allocation/freeing to consistently use the
     iommu-pages API and address-conversion helpers

   - Add PCI ATS infrastructure for devices that require ATS, including
     always-on ATS handling for pre-CXL devices

  AMD IOMMU:

   - Fix several IOTLB invalidation details, including PDE handling,
     flush-all behavior, and command address encoding

   - Honor IVINFO[VASIZE] when deriving address limits

   - Fix premature loop termination in init_iommu_one()

   - Add Hygon family 18h model 4h IOAPIC support

   - Clean up legacy-mode handling, stale comments, dead IVMD
     exclusion-range code, and unused address-size macros

  Arm SMMU / Arm SMMU v3:

   - SMMUv2:
      - Device-tree binding updates for Qualcomm Hawi, Nord and Shikra
        SoCs
      - Constrain the clocks which can be specified for recent Qualcomm
        SoCs
      - Fix broken compatible string for Qualcomm prefetcher
        configuration an add new entry for the Glymur MDSS
      - Ensure SMMU is powered-up when writing context bank for Adreno
        client

   - SMMUv3:
      - Fix off-by-one in queue allocation retry loop
      - Enable hardware update of access/dirty bits from the SMMU
      - Re-jig command construction to use separate inline helpers for
        each command type

  Intel VT-d:

   - Add the PCI segment number to DMA fault messages

   - Improve support for non-PRI mode SVA

   - Ensure atomicity during context entry teardown

   - Fix RB-tree corruption in the probe error path

  RISC-V IOMMU:

   - Add NAPOT range invalidation support

   - Use detailed gather information for invalidation decisions

   - Compute the best stride for single invalidations

   - Advertise Svpbmt support to the generic page-table code

   - Add capability definitions and clean up command macro encoding

  VeriSilicon IOMMU:

   - Add a new VeriSilicon IOMMU driver

   - Add devicetree binding documentation and MAINTAINERS coverage

   - Add the RK3588 VeriSilicon IOMMU node

   - Apply small cleanups and warning fixes in the new driver

  Rockchip IOMMU:

   - Disable the fetch DTE time limit

  Apple DART:

   - Correct a stale CONFIG_PCIE_APPLE macro name in a comment"

* tag 'iommu-updates-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (66 commits)
  iommu/dma-iommu: Fix wrong scatterlist length assignment in P2PDMA path
  iommu/amd: Control INVALIDATE_IOMMU_PAGES PDE from the gather
  iommu/amd: Make CMD_INV_IOMMU_ALL_PAGES_ADDRESS match the spec
  iommu/amd: Have amd_iommu_domain_flush_pages() use last
  iommu/amd: Pass last in through to build_inv_address()
  iommu/amd: Simplify build_inv_address()
  iommu/apple-dart: correct CONFIG_PCIE_APPLE macro name in comment
  iommu/vt-d: Fix RB-tree corruption in probe error path
  iommu/vt-d: Improve IOMMU fault information
  iommu/vt-d: Remove typo from pasid_pte_config_nested()
  iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
  iommu/vt-d: Avoid WARNING in sva unbind path
  dt-bindings: arm-smmu: Correct and add constraints for Hawi, Shikra and Kaanapali
  dt-bindings: arm-smmu: Add compatible for Qualcomm Nord SoC
  iommu/amd: Don't split flush for amd_iommu_domain_flush_all()
  iommu/rockchip: disable fetch dte time limit
  iommu/arm-smmu-v3: Allow ATS to be always on
  PCI: Allow ATS to be always on for pre-CXL devices
  PCI: Add pci_ats_required() for CXL.cache capable devices
  iommu/vsi: Use list_for_each_entry()
  ...

Merge branches 'apple/dart', 'arm/smmu/updates', 'arm/smmu/bindings', 'rockchip', 'verisilicon', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next

2026-06-12T12:57:23+00:00

dt-bindings: arm-smmu: Correct and add constraints for Hawi, Shikra and Kaanapali

2026-06-02T15:41:05+00:00

Previous commit 75949eb02653 ("dt-bindings: arm-smmu: Constrain clocks
for newer Qualcomm variants") duplicated constraints for
qcom,sm6350-smmu-500 and qcom,sm6375-smmu-500 - these are already part
of previous "if:" block.

It also missed enforcing one clock for qcom,kaanapali-smmu-500 in GPU
case and missed simultaneously added Shikra and Hawi.

Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Will Deacon

dt-bindings: arm-smmu: Add compatible for Qualcomm Nord SoC

2026-06-02T15:37:29+00:00

Document Applications Processor Subsystem (APSS) SMMU on Qualcomm
Nord SoC.

Signed-off-by: Shawn Guo 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Will Deacon

dt-bindings: iommu: riscv: Add bindings for Tenstorrent RISC-V IOMMU

2026-05-24T00:14:35+00:00

Extend the binding to cover details specific to the Tenstorrent RISC-V
IOMMU. In particular, a second register range is added which contains
M-privileged registers, e.g., PMAs and PMPs.

The RISC-V spec S-privileged registers remain in the first register
range and are compatible with "riscv,iommu" so the Linux driver does not
notice any difference, but the binding will be used by OpenSBI and
potentially other M-mode software.

Reviewed-by: Joel Stanley 
Acked-by: Conor Dooley 
Acked-by: Joerg Roedel 
Signed-off-by: Nicholas Piggin 
[fustini: fix dt_binding_check errors]
Signed-off-by: Drew Fustini

dt-bindings: arm-smmu: Constrain clocks for newer Qualcomm variants

2026-05-19T13:20:05+00:00

Many of SMMU on Qualcomm SoCs come in two flavors using the same front
compatible but a bit different fallback:

1. For application processor, usually without any controllable
   clocks,

2. For the Adreno GPU, with some controllable clock(s) and using
   additionally qcom,adreno-smmu fallback compatible.

Add missing constraints for Glymur SMMU on Adreno GPU and several other
Qualcomm SMMUs for application processors, to restrict the clocks
property to a specific length.

Acked-by: Rob Herring (Arm) 
Reviewed-by: Shawn Guo 
Signed-off-by: Krzysztof Kozlowski 
Signed-off-by: Will Deacon

dt-bindings: arm-smmu: Update the description for Glymur GPU SMMU

2026-05-19T12:08:31+00:00

Add the interconnects property to the common SMMU properties and extend
the sm8750 clock description section to also cover Glymur since it uses
the same single "hlos" vote clock.

Signed-off-by: Akhil P Oommen 
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Will Deacon

dt-bindings: arm-smmu: qcom: Add compatible for Qualcomm Shikra SoC

2026-05-19T11:53:07+00:00

Qualcomm Shikra SoC includes an apps SMMU that implements arm,mmu-500,
which is used to translate device-visible virtual addresses to physical
addresses. Add compatible for it.

Signed-off-by: Komal Bajaj 
Acked-by: Rob Herring (Arm) 
Signed-off-by: Will Deacon

dt-bindings: arm-smmu: qcom: Add Hawi compatible for Application processor

2026-05-19T10:41:37+00:00

Commit 5e8323c3d528 ("dt-bindings: arm-smmu: qcom: Add compatible for
Hawi SoC") was intended for the APSS SMMU but was mistakenly placed
under the Adreno GPU SMMU section. Since that compatible is also valid
for the Hawi GPU SMMU, keep that commit as-is and add proper
documentation for the Hawi APSS SMMU here.

Signed-off-by: Mukesh Ojha 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Will Deacon

dt-bindings: iommu: verisilicon: Add binding for VSI IOMMU

2026-05-11T08:00:58+00:00

Add a device tree binding for the Verisilicon (VSI) IOMMU.
This IOMMU sits in front of hardware encoder and decoder
blocks on SoCs using Verisilicon IP, such as the Rockchip RK3588.

Signed-off-by: Benjamin Gaignard 
Reviewed-by: Conor Dooley 
Signed-off-by: Joerg Roedel