linux-toradex.git/Documentation/devicetree/bindings/media/cdns,csi2rx.txt, branch master Linux kernel for Apalis and Colibri modules media: dt-bindings: cadence-csi2rx: Convert to DT schema 2023-07-14T10:38:10+00:00 Jack Zhu jack.zhu@starfivetech.com 2023-05-23T08:56:22+00:00 9536cc9492354a4dd8262aa2857a603ec3a0c77a Convert DT bindings document for Cadence MIPI-CSI2 RX controller to DT schema format. For compatible, new compatibles should not be messed with conversion, but the original binding did not specify any SoC-specific compatible string, so add the StarFive compatible string. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org> 
Convert DT bindings document for Cadence MIPI-CSI2 RX controller to
DT schema format.

For compatible, new compatibles should not be messed with conversion,
but the original binding did not specify any SoC-specific compatible
string, so add the StarFive compatible string.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
media: dt-bindings: media: Add Cadence MIPI-CSI2 RX Device Tree bindings 2018-05-16T15:08:35+00:00 Maxime Ripard maxime.ripard@bootlin.com 2018-05-04T14:08:07+00:00 3290aa63ee8088b74a1e4d6ec639272a47c8e9d7 The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Benoit Parrot <bparrot@ti.com> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> 
The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to
4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on
the hardware implementation.

It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Benoit Parrot <bparrot@ti.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>