Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Adding new device tree binding file for the DCSR node.  Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P4080, & P5020.

Signed-off-by: Stephen George <stephen.george@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards.  There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis".  Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.

We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed.  This means that older kernels are
not compatible with newer device trees.  This is not a real problem, however,
since that particular function doesn't work anyway.  When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Since technically it's not powerpc arch-specific.  Also rename it sec2
to differentiate it from its incompatible successor, the SEC 4.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>

Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com>
Acked-By: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Update the existing example in the general mpic binding to have a
separate TCRx region.  Currently the example doesn't describe TCRx at
all.  The one upstream device tree with an mpic timer node (p1022ds)
uses one large reg region to describe both, even though there are other
unrelated registers in between.  That device tree also contains a bogus
interrupt specifier, and there's no upstream software that uses this yet,
so changing this shouldn't be a problem.

Add a full binding for the MPIC timer node, not just an example of
4-cell interrupts in the MPIC binding.

Add fsl,available-ranges, similar to msi-available-ranges.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>

Adds binding documentation for cache sram for the PQ3 and some QorIQ
based platforms.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Define the binding for compatible = "fsl,mpic", including the definition
of 4-cell interrupt specifiers.  The 3rd and 4th cells are needed to
define additional types of interrupt source outside the "normal" external
and internal interrupts in FSL SoCs.  Define error interrupt, IPIs, and
PIC timer sources.

Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Now handles multiple ranges, doesn't make assumptions about interrupt
specifier format, and doesn't claim interrupts that don't correspond to an
available range.

Also has some better error checking.

The device tree binding is updated to clarify some existing assumptions.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>