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<title>linux-toradex.git/Documentation/devicetree/bindings/powerpc, branch v3.4.77</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>powerpc: document the FSL MPIC message register binding</title>
<updated>2012-03-16T21:15:28+00:00</updated>
<author>
<name>Jia Hongtao</name>
<email>B38951@freescale.com</email>
</author>
<published>2012-03-01T09:32:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=e96dde2b5edbc0d385ccced05fb5db68c070b0d4'/>
<id>e96dde2b5edbc0d385ccced05fb5db68c070b0d4</id>
<content type='text'>
This binding documents how the message register blocks found in some FSL
MPIC implementations shall be represented in a device tree.

Signed-off-by: Meador Inge &lt;meador_inge@mentor.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This binding documents how the message register blocks found in some FSL
MPIC implementations shall be represented in a device tree.

Signed-off-by: Meador Inge &lt;meador_inge@mentor.com&gt;
Signed-off-by: Jia Hongtao &lt;B38951@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/fsl: Added aliased MSIIR register address to MSI node in dts</title>
<updated>2012-03-16T21:15:19+00:00</updated>
<author>
<name>Diana CRACIUN</name>
<email>Diana.Craciun@freescale.com</email>
</author>
<published>2012-02-01T15:50:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=da3b6c0534c76bc08ce5524342586138687fd106'/>
<id>da3b6c0534c76bc08ce5524342586138687fd106</id>
<content type='text'>
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = &lt;0x41600 0x200 0x44140 4&gt;;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.

Signed-off-by: Diana CRACIUN &lt;Diana.Craciun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The MSIIR register for each MSI bank is aliased to a different
address. The MSI node reg property was updated to contain this
address:

e.g. reg = &lt;0x41600 0x200 0x44140 4&gt;;

The first region contains the address and length of the MSI
register set and the second region contains the address of
the aliased MSIIR register at 0x44140.

Signed-off-by: Diana CRACIUN &lt;Diana.Craciun@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/mpic: Add "last-interrupt-source" property to override hardware</title>
<updated>2012-02-22T23:50:00+00:00</updated>
<author>
<name>Kyle Moffett</name>
<email>Kyle.D.Moffett@boeing.com</email>
</author>
<published>2011-12-22T10:19:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=c1b8d45db4dbc64cc6015f97922f767fdf782f64'/>
<id>c1b8d45db4dbc64cc6015f97922f767fdf782f64</id>
<content type='text'>
The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not
correctly report the number of hardware interrupt sources, so software
needs to override the detected value with "256".

To avoid needing to write custom board-specific code to detect that
scenario, allow it to be easily overridden in the device-tree.

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The FreeScale PowerQUICC-III-compatible (mpc85xx/mpc86xx) MPICs do not
correctly report the number of hardware interrupt sources, so software
needs to override the detected value with "256".

To avoid needing to write custom board-specific code to detect that
scenario, allow it to be easily overridden in the device-tree.

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/mpic: Create and document the "single-cpu-affinity" device-tree flag</title>
<updated>2012-02-22T23:49:59+00:00</updated>
<author>
<name>Kyle Moffett</name>
<email>Kyle.D.Moffett@boeing.com</email>
</author>
<published>2011-12-22T10:19:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=9ca163c8602681ad098910f48f89b97f0cb87c4f'/>
<id>9ca163c8602681ad098910f48f89b97f0cb87c4f</id>
<content type='text'>
The Freescale MPIC (and perhaps others in the future) is incapable of
routing non-IPI interrupts to more than once CPU at a time.  Currently
all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to
mpic_alloc(), but that information should really be present in the
device-tree.

Older board code can't rely on the device-tree having the property set,
but newer platforms won't need it manually specified in the code.

[BenH: Remove unrelated changes, folded in a different patch]

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The Freescale MPIC (and perhaps others in the future) is incapable of
routing non-IPI interrupts to more than once CPU at a time.  Currently
all of the Freescale boards msut pass the MPIC_SINGLE_DEST_CPU flag to
mpic_alloc(), but that information should really be present in the
device-tree.

Older board code can't rely on the device-tree having the property set,
but newer platforms won't need it manually specified in the code.

[BenH: Remove unrelated changes, folded in a different patch]

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>fsl/mpic: Document and use the "big-endian" device-tree flag</title>
<updated>2012-02-22T23:49:58+00:00</updated>
<author>
<name>Kyle Moffett</name>
<email>Kyle.D.Moffett@boeing.com</email>
</author>
<published>2011-12-22T10:19:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=98cca250aecaf3f1b2fec003e1c0ce0bfaa4be36'/>
<id>98cca250aecaf3f1b2fec003e1c0ce0bfaa4be36</id>
<content type='text'>
The MPIC code checks for a "big-endian" property and sets the flag
MPIC_BIG_ENDIAN if one is present, although prior to the "mpic-&gt;flags"
fixup that would never have worked anways.

Unfortunately, even now that it works properly, the Freescale mpic
device-node (the "PowerQUICC-III"-compatible one) does not specify it,
so all of the board ports need to manually pass it to mpic_alloc().

Document the flag and add it to the pq3 device tree.  Existing code will
still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not
have this property, but new platforms shouldn't need to do so.

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The MPIC code checks for a "big-endian" property and sets the flag
MPIC_BIG_ENDIAN if one is present, although prior to the "mpic-&gt;flags"
fixup that would never have worked anways.

Unfortunately, even now that it works properly, the Freescale mpic
device-node (the "PowerQUICC-III"-compatible one) does not specify it,
so all of the board ports need to manually pass it to mpic_alloc().

Document the flag and add it to the pq3 device tree.  Existing code will
still need to pass the MPIC_BIG_ENDIAN flag because their dtb may not
have this property, but new platforms shouldn't need to do so.

Signed-off-by: Kyle Moffett &lt;Kyle.D.Moffett@boeing.com&gt;
Signed-off-by: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/fsl: Document rapidio node binding-information</title>
<updated>2011-11-24T08:01:34+00:00</updated>
<author>
<name>Liu Gang</name>
<email>Gang.Liu@freescale.com</email>
</author>
<published>2011-11-12T12:02:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=91610d830dbc90ebf01fd255873d8277bf72d040'/>
<id>91610d830dbc90ebf01fd255873d8277bf72d040</id>
<content type='text'>
This document is created for powerpc rapidio and rmu nodes in dts file.
These nodes can support two rapidio ports and message units. In addition,
It explicates the properties and gives examples about rapidio and rmu nodes.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jin Qing &lt;b24347@freescale.com&gt;
Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Acked-by: Alexandre Bounine &lt;alexandre.bounine@idt.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This document is created for powerpc rapidio and rmu nodes in dts file.
These nodes can support two rapidio ports and message units. In addition,
It explicates the properties and gives examples about rapidio and rmu nodes.

Signed-off-by: Li Yang &lt;leoli@freescale.com&gt;
Signed-off-by: Jin Qing &lt;b24347@freescale.com&gt;
Signed-off-by: Liu Gang &lt;Gang.Liu@freescale.com&gt;
Acked-by: Alexandre Bounine &lt;alexandre.bounine@idt.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/fsl_msi: add support for "msi-address-64" property</title>
<updated>2011-10-14T07:54:29+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2011-09-23T17:41:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=2bcd1c0cfcf53a384159c272c972645e7e822140'/>
<id>2bcd1c0cfcf53a384159c272c972645e7e822140</id>
<content type='text'>
Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add support for the msi-address-64 property of a PCI node.  This property
specifies the PCI address of MSIIR (message signaled interrupt index
register).

In commit 3da34aae ("powerpc/fsl: Support unique MSI addresses per PCIe Root
Complex"), the msi_addr_hi/msi_addr_lo fields of struct fsl_msi were redefined
from an actual address to just an offset, but the fields were not renamed
accordingly.  These fields are replace with a single field, msiir_offset,
to reflect the new meaning.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: Adding DCSR node to dtsi device trees</title>
<updated>2011-10-12T04:47:29+00:00</updated>
<author>
<name>Stephen George</name>
<email>stephen.george@freescale.com</email>
</author>
<published>2011-09-16T15:36:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=b9df02231930c01eaaf3c37b192bd75ea0d1c0bb'/>
<id>b9df02231930c01eaaf3c37b192bd75ea0d1c0bb</id>
<content type='text'>
Adding new device tree binding file for the DCSR node.  Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P4080, &amp; P5020.

Signed-off-by: Stephen George &lt;stephen.george@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Adding new device tree binding file for the DCSR node.  Modifying device
tree dtsi files to add DCSR node for P2041, P3041, P4080, &amp; P5020.

Signed-off-by: Stephen George &lt;stephen.george@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>powerpc/85xx: clean up FPGA device tree nodes for Freecsale QorIQ boards</title>
<updated>2011-10-12T04:47:24+00:00</updated>
<author>
<name>Timur Tabi</name>
<email>timur@freescale.com</email>
</author>
<published>2011-09-15T18:04:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=499ccb27a89ecd08475f73710fe27fb600431a91'/>
<id>499ccb27a89ecd08475f73710fe27fb600431a91</id>
<content type='text'>
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards.  There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis".  Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.

We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed.  This means that older kernels are
not compatible with newer device trees.  This is not a real problem, however,
since that particular function doesn't work anyway.  When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Standarize and document the FPGA nodes used on Freescale QorIQ reference
boards.  There are different kinds of FPGAs used on the boards, but
only two are currently standard: "pixis", "ngpixis", and "qixis".  Although
there are minor differences among the boards that have one kind of FPGA, most
of the functionality is the same, so it makes sense to create common
compatibility strings.

We also need to update the P1022DS platform file, because the compatible
string for its PIXIS node has changed.  This means that older kernels are
not compatible with newer device trees.  This is not a real problem, however,
since that particular function doesn't work anyway.  When the DIU is active,
the PIXIS is in "indirect mode", and so cannot be accessed as a memory-mapped
device.

Signed-off-by: Timur Tabi &lt;timur@freescale.com&gt;
Signed-off-by: Kumar Gala &lt;galak@kernel.crashing.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt: bindings: move SEC node under new crypto/</title>
<updated>2011-07-07T19:51:19+00:00</updated>
<author>
<name>Kim Phillips</name>
<email>kim.phillips@freescale.com</email>
</author>
<published>2011-07-07T19:43:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=5a9ebe959967b7d3579de2a53d5df470fe0c7f22'/>
<id>5a9ebe959967b7d3579de2a53d5df470fe0c7f22</id>
<content type='text'>
Since technically it's not powerpc arch-specific.  Also rename it sec2
to differentiate it from its incompatible successor, the SEC 4.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Since technically it's not powerpc arch-specific.  Also rename it sec2
to differentiate it from its incompatible successor, the SEC 4.

Signed-off-by: Kim Phillips &lt;kim.phillips@freescale.com&gt;
Signed-off-by: Grant Likely &lt;grant.likely@secretlab.ca&gt;
</pre>
</div>
</content>
</entry>
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