linux-toradex.git/Documentation/devicetree/bindings/usb, branch v6.8

Merge tag 'devicetree-fixes-for-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2024-02-15T18:19:55+00:00

Pull devicetree fixes from Rob Herring:

 - Improve devlink dependency parsing for DT graphs

 - Fix devlink handling of io-channels dependencies

 - Fix PCI addressing in marvell,prestera example

 - A few schema fixes for property constraints

 - Improve performance of DT unprobed devices kselftest

 - Fix regression in DT_SCHEMA_FILES handling

 - Fix compile error in unittest for !OF_DYNAMIC

* tag 'devicetree-fixes-for-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  dt-bindings: ufs: samsung,exynos-ufs: Add size constraints on "samsung,sysreg"
  of: property: Add in-ports/out-ports support to of_graph_get_port_parent()
  of: property: Improve finding the supplier of a remote-endpoint property
  of: property: Improve finding the consumer of a remote-endpoint property
  net: marvell,prestera: Fix example PCI bus addressing
  of: unittest: Fix compile in the non-dynamic case
  of: property: fix typo in io-channels
  dt-bindings: tpm: Drop type from "resets"
  dt-bindings: display: nxp,tda998x: Fix 'audio-ports' constraints
  dt-bindings: xilinx: replace Piyush Mehta maintainership
  kselftest: dt: Stop relying on dirname to improve performance
  dt-bindings: don't anchor DT_SCHEMA_FILES to bindings directory

dt-bindings: xilinx: replace Piyush Mehta maintainership

2024-01-31T13:42:38+00:00

As Piyush is leaving AMD, he handed over ahci-ceva, ZynqMP Mode Pin GPIO
controller, Zynq UltraScale+ MPSoC and Versal reset, Xilinx SuperSpeed
DWC3 USB SoC controller, Microchip USB5744 4-port Hub Controller and
Xilinx udc controller maintainership duties to Mubin and Radhey.

Signed-off-by: Radhey Shyam Pandey 
Acked-by: Mubin Sayyed 
Acked-by: Michal Simek 
Acked-by: Krzysztof Kozlowski 
Acked-by: Piyush Mehta 
Acked-by: Bartosz Golaszewski 
Acked-by: Niklas Cassel 
Link: https://lore.kernel.org/r/1705664181-722937-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Rob Herring

dt-bindings: usb: dwc3: Limit num-hc-interrupters definition

2024-01-04T15:09:29+00:00

Ensure that the number of XHCI secondary interrupters defined for a DWC3
based implementation is limited to 8.  XHCI in general can potentially
support up to 1024 interrupters.

Reviewed-by: Rob Herring 
Signed-off-by: Wesley Cheng 
Link: https://lore.kernel.org/r/20240102214549.22498-16-quic_wcheng@quicinc.com
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: xhci: Add num-hc-interrupters definition

2024-01-04T15:09:27+00:00

Add the definition for how many interrupts the XHCI host controller should
allocate.  XHCI can potentially support up to 1024 interrupters, which
implementations may want to limit.

Reviewed-by: Rob Herring 
Signed-off-by: Wesley Cheng 
Link: https://lore.kernel.org/r/20240102214549.22498-15-quic_wcheng@quicinc.com
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: mtk-xhci: add a property for Gen1 isoc-in transfer issue

2024-01-04T15:05:50+00:00

For Gen1 isoc-in endpoint on controller before about SSUSB IPM v1.6.0, it
still send out unexpected ACK after receiving a short packet in burst
transfer, this will cause an exception on connected device, specially for
a 4k camera.
Add a quirk property "rx-fifo-depth" to work around this hardware issue,
prefer to use 3k bytes;
The side-effect is that it may cause performance drop about 10%, including
bulk transfer.

Acked-by: Krzysztof Kozlowski 
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Chunfeng Yun 
Link: https://lore.kernel.org/r/20240104061640.7335-1-chunfeng.yun@mediatek.com
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: qcom,dwc3: Fix SDM660 clock description

2024-01-04T15:05:28+00:00

SDM660 was abusingly referencing one of the internal bus clocks, that
were recently dropped from Linux (because the original implementation
did not make much sense), circumventing the interconnect framework.

Drop it.

Signed-off-by: Konrad Dybcio 
Acked-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20230721-topic-rpm_clk_cleanup-v3-1-a66e698932e3@linaro.org
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: dwc3: Clean up hs_phy_irq in binding

2024-01-04T15:04:50+00:00

The high speed related interrupts present on QC targets are as follows:

1. dp/dm irq's
These IRQ's directly reflect changes on the DP/DM pads of the SoC. These
are used as wakeup interrupts only on SoCs with non-QUSB2 targets with
exception of SDM670/SDM845/SM6350.

2. qusb2_phy irq
SoCs with QUSB2 PHY do not have separate DP/DM IRQs and expose only a
single IRQ whose behavior can be modified by the QUSB2PHY_INTR_CTRL
register. The required DPSE/DMSE configuration is done in
QUSB2PHY_INTR_CTRL register of phy address space.

3. hs_phy_irq
This is completely different from the above two and is present on all
targets with exception of a few IPQ ones. The interrupt is not enabled by
default and its functionality is mutually exclusive of qusb2_phy on QUSB
targets and DP/DM on femto phy targets.

The DTs of several QUSB2 PHY based SoCs incorrectly define "hs_phy_irq"
when they should have been "qusb2_phy_irq". On Femto phy targets, the
"hs_phy_irq" mentioned is either the actual "hs_phy_irq" or "pwr_event",
neither of which would never be triggered directly are non-functional
currently. The implementation tries to clean up this issue by addressing
the discrepencies involved and fixing the hs_phy_irq's in respective DT's.

Classify SoC's into four groups based on whether qusb2_phy interrupt
or {dp/dm}_hs_phy_irq is used for wakeup in high speed and whether the
SoCs have hs_phy_irq present in them or not. The ss_phy_irq is optional
interrupt because there are mutliple SoC's which either support only High
Speed or there are multiple controllers within same Soc and the secondary
controller is High Speed only capable.

This breaks ABI on targets running older kernels, but since the interrupt
definitions are given wrong on many targets and to establish proper rules
for usage of DWC3 interrupts on Qualcomm platforms, DT binding update is
necessary. The bindings put pwr_event as the first interrupt and ss_phy as
the last. Since all SoCs have the pwr_event (HS) interrupt, but not all
controllers have the SS PHY interrupt, this would prevent, to some extent,
expressing that the SS PHY is optional by keeping it last in the binding
schema and making sure that minItems = maxItems - 1.

No new targets have been added to schema. Only the existing ones have been
re-ordered.

Signed-off-by: Krishna Kurapati 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20231227091951.685-2-quic_kriskura@quicinc.com
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: qcom,dwc3: Add X1E80100 binding

2023-12-15T12:56:12+00:00

Add X1E80100 to the DT schema.

Signed-off-by: Abel Vesa 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20231214-x1e80100-usb-v1-1-c22be5c0109e@linaro.org
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: Document WCD939x USB SubSystem Altmode/Analog Audio Switch

2023-12-15T12:54:13+00:00

Document the Qualcomm WCD9390/WCD9395 USB SubSystem Altmode/Analog Audio Switch
which is a separate USB SubSystem for Altmode/Analog Audio Switch accessible
over an I2C interface.

Since Audio Headphone and Microphone data path between the Codec and the USB-C Mux
subsystems are external to the IC, it requires a second port to handle USB-C altmode
& orientation switching for Audio Accessory Mode to the Codec SubSystem.

Signed-off-by: Neil Armstrong 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20231212-topic-sm8650-upstream-wcd939x-usbss-v2-1-38961fea5867@linaro.org
Signed-off-by: Greg Kroah-Hartman

dt-bindings: usb: nxp,ptn5110: Fix typos in the title

2023-12-15T12:52:59+00:00

Fix the misspelled "Controller" and "Type-C" words.

Signed-off-by: Fabio Estevam 
Acked-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20231207172912.2658226-1-festevam@gmail.com
Signed-off-by: Greg Kroah-Hartman