linux-toradex.git/Documentation/driver-api/cxl/platform, branch master Linux kernel for Apalis and Colibri modules Documentation/driver-api/cxl: device hotplug section 2026-01-22T23:58:13+00:00 Gregory Price gourry@gourry.net 2025-12-19T17:05:38+00:00 7362facf6ec14f70fe28413cb484639d783b89f0 Describe cxl memory device hotplug implications, in particular how the platform CEDT CFMWS must be described to support successful hot-add of memory devices. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alejandro Lucero Palau <alucerop@amd.com> Link: https://patch.msgid.link/20251219170538.1675743-3-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Describe cxl memory device hotplug implications, in particular how the
platform CEDT CFMWS must be described to support successful hot-add of
memory devices.

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alejandro Lucero Palau <alucerop@amd.com>
Link: https://patch.msgid.link/20251219170538.1675743-3-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation/driver-api/cxl: BIOS/EFI expectation update 2026-01-22T23:58:13+00:00 Gregory Price gourry@gourry.net 2025-12-19T17:05:37+00:00 2489d83c22ce9e44425469960677e6dbfd68adcc Add a snippet about what Linux expects BIOS/EFI to do (and not to do) to the BIOS/EFI section. Suggested-by: Alejandro Lucero Palau <alucerop@amd.com> Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Alejandro Lucero Palau <alucerop@amd.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20251219170538.1675743-2-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add a snippet about what Linux expects BIOS/EFI to do (and not
to do) to the BIOS/EFI section.

Suggested-by: Alejandro Lucero Palau <alucerop@amd.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Alejandro Lucero Palau <alucerop@amd.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20251219170538.1675743-2-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Merge tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl 2025-10-04T19:02:50+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-04T19:02:50+00:00 d104e3d17f7bfc505281f57f8c1a5589fca6ffe4 Pull CXL updates from Dave Jiang: "The changes include adding poison injection support, fixing CXL access coordinates when onlining CXL memory, and delaing the enumeration of downstream switch ports for CXL hierarchy to ensure that the CXL link is established at the time of enumeration to address a few issues observed on AMD and Intel platforms. Misc changes: - Use str_plural() instead of open code for emitting strings. - Use str_enabled_disabled() instead of ternary operator - Fix emit of type resource_size_t argument for validate_region_offset() - Typo fixup in CXL driver-api documentation - Rename CFMWS coherency restriction defines - Add convention doc describe dealing with x86 low memory hole and CXL Poison Inject support: - Move hpa_to_spa callback to new reoot decoder ops structure - Define a SPA to HPA callback for interleave calculation with XOR math - Add support for SPA to DPA address translation with XOR - Add locked variants of poison inject and clear functions - Add inject and clear poison support by region offset CXL access coordinates update fix: - A comment update for hotplug memory callback prority defines - Add node_update_perf_attrs() for updating perf attrs on a node - Update cxl_access_coordinates() to use the new node update function - Remove hmat_update_target_coordinates() and related code CXL delayed downstream port enumeration and initialization: - Add helper to detect top of CXL device topology and remove open coding - Add helper to delete single dport - Add a cached copy of target_map to cxl_decoder - Refactor decoder setup to reduce cxl_test burden - Defer dport allocation for switch ports - Add mock version of devm_cxl_add_dport_by_dev() for cxl_test - Adjust the mock version of devm_cxl_switch_port_decoders_setup() due to cxl core usage - Setup target_map for cxl_test decoder initialization - Change SSLBIS handler to handle single dport - Move port register setup to when first dport appears" * tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits) cxl: Move port register setup to when first dport appear cxl: Change sslbis handler to only handle single dport cxl/test: Setup target_map for cxl_test decoder initialization cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup() cxl/test: Add mock version of devm_cxl_add_dport_by_dev() cxl: Defer dport allocation for switch ports cxl/test: Refactor decoder setup to reduce cxl_test burden cxl: Add a cached copy of target_map to cxl_decoder cxl: Add helper to delete dport cxl: Add helper to detect top of CXL device topology cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution cxl/acpi: Rename CFMW coherency restrictions Documentation/driver-api: Fix typo error in cxl acpi/hmat: Remove now unused hmat_update_target_coordinates() cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT drivers/base/node: Add a helper function node_update_perf_attrs() mm/memory_hotplug: Update comment for hotplug memory callback priorities cxl: Fix emit of type resource_size_t argument for validate_region_offset() cxl/region: Add inject and clear poison by region offset cxl/core: Add locked variants of the poison inject and clear funcs ... 
Pull CXL updates from Dave Jiang:
 "The changes include adding poison injection support, fixing CXL access
  coordinates when onlining CXL memory, and delaing the enumeration of
  downstream switch ports for CXL hierarchy to ensure that the CXL link
  is established at the time of enumeration to address a few issues
  observed on AMD and Intel platforms.

  Misc changes:
   - Use str_plural() instead of open code for emitting strings.
   - Use str_enabled_disabled() instead of ternary operator
   - Fix emit of type resource_size_t argument for
     validate_region_offset()
   - Typo fixup in CXL driver-api documentation
   - Rename CFMWS coherency restriction defines
   - Add convention doc describe dealing with x86 low memory hole
     and CXL

  Poison Inject support:
   - Move hpa_to_spa callback to new reoot decoder ops structure
   - Define a SPA to HPA callback for interleave calculation with
     XOR math
   - Add support for SPA to DPA address translation with XOR
   - Add locked variants of poison inject and clear functions
   - Add inject and clear poison support by region offset

  CXL access coordinates update fix:
   - A comment update for hotplug memory callback prority defines
   - Add node_update_perf_attrs() for updating perf attrs on a node
   - Update cxl_access_coordinates() to use the new node update function
   - Remove hmat_update_target_coordinates() and related code

  CXL delayed downstream port enumeration and initialization:
   - Add helper to detect top of CXL device topology and remove
     open coding
   - Add helper to delete single dport
   - Add a cached copy of target_map to cxl_decoder
   - Refactor decoder setup to reduce cxl_test burden
   - Defer dport allocation for switch ports
   - Add mock version of devm_cxl_add_dport_by_dev() for cxl_test
   - Adjust the mock version of devm_cxl_switch_port_decoders_setup()
     due to cxl core usage
   - Setup target_map for cxl_test decoder initialization
   - Change SSLBIS handler to handle single dport
   - Move port register setup to when first dport appears"

* tag 'cxl-for-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (25 commits)
  cxl: Move port register setup to when first dport appear
  cxl: Change sslbis handler to only handle single dport
  cxl/test: Setup target_map for cxl_test decoder initialization
  cxl/test: Adjust the mock version of devm_cxl_switch_port_decoders_setup()
  cxl/test: Add mock version of devm_cxl_add_dport_by_dev()
  cxl: Defer dport allocation for switch ports
  cxl/test: Refactor decoder setup to reduce cxl_test burden
  cxl: Add a cached copy of target_map to cxl_decoder
  cxl: Add helper to delete dport
  cxl: Add helper to detect top of CXL device topology
  cxl: Documentation/driver-api/cxl: Describe the x86 Low Memory Hole solution
  cxl/acpi: Rename CFMW coherency restrictions
  Documentation/driver-api: Fix typo error in cxl
  acpi/hmat: Remove now unused hmat_update_target_coordinates()
  cxl, acpi/hmat: Update CXL access coordinates directly instead of through HMAT
  drivers/base/node: Add a helper function node_update_perf_attrs()
  mm/memory_hotplug: Update comment for hotplug memory callback priorities
  cxl: Fix emit of type resource_size_t argument for validate_region_offset()
  cxl/region: Add inject and clear poison by region offset
  cxl/core: Add locked variants of the poison inject and clear funcs
  ...
Documentation/driver-api: Fix typo error in cxl 2025-09-10T15:07:14+00:00 Rakuram Eswaran rakuram.e96@gmail.com 2025-08-18T17:53:34+00:00 a414408126d13d6d5b2d2c4e537295771cc256cb Fixed the following typo errors intersparsed ==> interspersed in Documentation/driver-api/cxl/platform/bios-and-efi.rst Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250818175335.5312-1-rakuram.e96@gmail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Fixed the following typo errors

intersparsed ==> interspersed
in Documentation/driver-api/cxl/platform/bios-and-efi.rst

Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250818175335.5312-1-rakuram.e96@gmail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation: Fix driver-api typos 2025-08-18T16:17:49+00:00 Ranganath V N vnranganath.20@gmail.com 2025-08-14T18:43:03+00:00 6cf5f13ef3f1c032b48fddd4f0f9108236c7762a Corrected a few spelling mistakes functionalty ==> functionality in Documentation/driver-api/cxl/devices/device-types.rst adjascent ==> adjacent in Documentation/driver-api/cxl/platform/example-configurations/one-dev-per-hb.rst succeessful ==> successful in Documentation/driver-api/thermal/exynos_thermal_emulation.rst Signed-off-by: Ranganath V N <vnranganath.20@gmail.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net> Link: https://lore.kernel.org/r/20250814184304.20448-1-vnranganath.20@gmail.com 
Corrected a few spelling mistakes

functionalty ==> functionality
in Documentation/driver-api/cxl/devices/device-types.rst

adjascent ==> adjacent
in Documentation/driver-api/cxl/platform/example-configurations/one-dev-per-hb.rst

succeessful ==> successful
in Documentation/driver-api/thermal/exynos_thermal_emulation.rst

Signed-off-by: Ranganath V N <vnranganath.20@gmail.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Link: https://lore.kernel.org/r/20250814184304.20448-1-vnranganath.20@gmail.com
cxl: docs/platform/acpi/srat Add generic target documentation 2025-05-15T23:39:13+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:22+00:00 1ce91b37b2661ebeca71982eadf3e3d5e0584a2f Add description in the SRAT document to describe the Generic Port Affinity sub-table. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add description in the SRAT document to describe the Generic Port
Affinity sub-table.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/cdat reference documentation 2025-05-15T23:39:12+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:21+00:00 49cee8fe5e6c6af2c6a76448840ae2eef9641084 Add documentation for CDAT structures for CXL usages. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add documentation for CDAT structures for CXL usages.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs - add self-referencing cross-links 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:34+00:00 dba600d0f2e9d2dea53891d95f1ff38d3e089275 Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add some crosslinks between pages in the CXL docs - mostly to the
ACPI tables.

Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/example-configs documentation 2025-05-13T20:07:45+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:23+00:00 8545940bd420e7a79c66bccee330a947581d259b Add example ACPI Table configurations for different sample platforms. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-7-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add example ACPI Table configurations for different sample platforms.

Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-7-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/acpi reference documentation 2025-05-13T20:07:45+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:22+00:00 d1ba364627d5dc3429735c846ca2a8ea925073bd Add basic ACPI table information needed to understand the CXL driver probe process. Signed-off-by: Gregory Price <gourry@gourry.net> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512162134.3596150-6-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add basic ACPI table information needed to understand the CXL
driver probe process.

Signed-off-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512162134.3596150-6-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>