DRM Rust changes for v7.4-rc1

- Cross-subsystem:

  - I/O (shared from driver-core tree via signed tag rust-io-7.4-rc1):

    - Reimplement register!() as a procedural macro, require matching
      base types for register access, and replace relative registers
      with typed I/O projections. Convert Nova, Tyr and the PCI sample

    - Add AsRepr/AsReprMut conversions for I/O on compatible wrapper
      types and transmute helpers with deferred size checks

  - DMA (shared from driver-core tree via signed tag rust-dma-7.4-rc1):

    - Tie Coherent, CoherentBox and CoherentHandle to the device's bound
      lifetime, and allow scoped debugfs files backed by non-'static
      data

  - Allow auxiliary registration-data closures to return covariant
    sub-fields and add UserSliceWriter::write_truncated()

  - Implement Send and Sync for MapleTree

  - Add PCI resource_flags() and IORESOURCE_MEM_64, and convert PCI IRQ
    flags to impl_flags!()

  - Add I/O view cast() with compile-time size and alignment checks

- DRM:

  - Add Rust dma_fence abstractions with separate producer (DriverFence)
    and consumer (Fence) types, per-context sequencing, signal callbacks
    and preallocation. Additional backend operations remain follow-up
    work.

  - Initialize DRM registrations and their data in place, removing a
    separate allocation

  - Drop the unused flags argument from drm::Registration::new()

- Nova:

  - UAPI and Cross Module API:
    - Add NovaCoreApi and a lifetime-bound handle for auxiliary child
      drivers, carried in nova-drm registration data
    - Expose a render node and extensible INFO ioctl reporting GPU
      architecture, opaque chip ID, usable VRAM and VRAM BAR sizes,
      full and short GPU names, and GID, with size discovery and
      truncation to the userspace buffer size
    - Move BAR-size queries into GPU info, removing GETPARAM and
      changing the UAPI

  - PRAMIN access:
    - Add typed CPU access to VRAM through the movable 1 MiB BAR0
      PRAMIN window, with per-architecture support from Turing through
      Blackwell
    - Add GpuMm centralized memory manager, VramAddress type, aperture
      documentation and optional probe-time self-tests under
      CONFIG_NOVA_CORE_SELFTESTS

  - GPU virtual memory and BAR1:
    - Add VRAM buddy allocation, TLB flushing, MMU v2/v3 page-table
      types with trait-based generics (PteOps, PdeOps, DualPdeOps,
      MmuConfig) and a generic walker
    - Add maple-tree virtual address tracking and multi-page mapping,
      separating allocation from mapping execution
    - Add CPU access to mapped VRAM through BAR1 and memory-management
      self-tests; handle 64-bit BAR0 when locating BAR1

  - GPU interrupts and GSP events:
    - Add GIN (GPU Interrupt and Notification) interrupt-tree support
      with MSI-X, MSI fallback and per-architecture rearming
    - Drain GSP events between commands via a threaded SWGEN0 handler
    - Report OS errors, robust-channel notifications and unknown
      messages without aborting command waits; hold the queue lock and
      use one deadline per wait
    - Disable GSP event interrupts on persistent falcon faults or
      drain errors
    - Add a delivery/rearm self-test, interrupt-tree KUnit coverage
      and interrupt-controller documentation

  - GSP messaging fixes:
    - Queue setup RPCs before GSP-RM boot
    - Correct DMA barriers in both queue directions

  - Firmware and transport:
    - Extract a reusable radix3 buffer mapper; zero-pad page-table
      levels to whole pages to prevent booter reads of stale padding
    - Correct GSP-FMC naming and boot-flow documentation
    - Set MCTP header version 1 for FSP messages and retain the
      command queue's BAR0 reference

  - Resource handling:
    - Replace unnecessary BarUser reference counting with in-place
      ownership and borrowed access; consolidate probe initialization
    - Declare an unlimited DMA maximum segment size

- Tyr:

  - Use bitfield!() for firmware section flags and memory attributes
    that do not describe registers

  - Zero unsupported and newly added GPU-info fields, and limit the
    doorbell array to 17 entries to fit the mapped register region

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: "Danilo Krummrich" <dakr@kernel.org>
Link: https://patch.msgid.link/DM371PN4TBJT.3LY1B0EYWSI4@kernel.org

drm-misc-next for v7.4:

Cross-subsystem Changes:

Documentation:
- Fix indention in display-related DT bindings

Core Changes:

- Provide helpers for calculating absolute and relative timeouts

clients:
- fbdev: Move helpers from drm_kms_helper.ko to drm_client_lib.ko

display:
- dp/mst: Improve DPCD compliance

sched:
- fix locking

Driver changes:
amdxdna:
- Support AIE2 rev 9
- Fix UAF access in scheduler fences
- Update workqueue interface

bridge:
- Select DRM_PANEL_BRIDGE for various drivers that require it

host1x:
- Support partitioning

imagination
- Clean up firmware interface

imx:
- Replace simple-display with regular atomic helpers

ivpu:
- Simplify NULL-pointer handling in cleanup code

mxsfb:
- Support bus formats plus DT bindings

panel:
- ebbg-ft8719: Fix MODULE_LICENSE() string; Improve initialization
- edp: NV140WU2-M70
- ilitek-ili9882t: Support Ilitek IL79600A plus DT bindings
- simple: Support Truly TFT320240-229-E plus DT bindings; Support BOE
  DV215FHM-R01 plus DT bindings
- Refactor struct drm_panel to contain struct drm_bridge plus fallout in
  various panel drivers

panthor:
- Validate user-space input against firmware limits

renesas:
- Support RZ/G3L SoC

ssd130x:
- ssd132x: Set correct hardware window when clearing screen

host1x:
- support partitioning

panel:
- fix fallout from bridge-related changes

tegra:
- improve syncobj handling on submit

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patch.msgid.link/20261002120720.GA720384@linux.fritz.box

The interrupt code rests on hardware behavior that the code cannot show
on its own: how GIN, the GPU's interrupt controller, records and
delivers interrupts, what edge-triggered delivery requires of a handler,
and how the GSP signals the CPU. Some of those requirements come from
OpenRM rather than from the hardware manuals.

Add a design document that records that behavior, the rules that
nova-core follows because of it, and the terms that the code uses for
it. The code comments cite the document by section rather than repeating
it.

Assisted-by: LLM
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Link: https://patch.msgid.link/20260930034148.590687-16-jhubbard@nvidia.com
[acourbot: cut the last 3 sections.]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>

UAPI Changes:
 - New sysfs to expose device UID (Badal)

Driver Changes:
 - Nuke PTs only after unlinking contested VMAs (Auld)
 - Limit sg segment size to PAGE_SIZE on Xen PV (Szymon)
 - Move locking to xe_sriov_pf_reprovision_default (Michal)
 - New workarounds (Tilak, Tales, Daniel)
 - Keep VF LMEM BAR size low if no VFs enabled (Marcin)
 - Drop ratelimiting from dev_unhold_work debug trace (Varun)
 - System Controller's Maibox response improvement (Anoop)
 - General clean-ups (Roper, Lin)
 - Revert "drm/xe: Set mask bits for CCS_MODE register" (Roper)
 - CPU binds and ULLS on migration queue (Brost)
 - Re-apply an i2c patch silently removed by a merge (Bartosz)
 - New PTL PCI ID (Atwood)
 - Enable PXP for NVL-S (Alan)
 - Let xe_guc_ct_send_locked() callers reserve G2H credit (Sujaritha)
 - Implement print vfunc for page fault info logging (Brian)
 - Do not dma_fence_put zero fences in err_out path (Jonathan)
 - Add focused VM teardown and page fault tracing (Daniel)
 - Fix ULLS chained job loss and GT reset replay (Varun)
 - Refresh TTM LRU on SVM prefetch (Himal)
 - Fix xe_mmio_wait32() to honor delay/sleep maximums (Alan)

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/ar5YsqAK3bS4Ta6Z@intel.com

The source file location was changed, so update the documentation
accordingly. Fixes these warnings:

ERROR: Cannot find file ../drivers/gpu/drm/bridge/panel.c
ERROR: Cannot find file ../drivers/gpu/drm/bridge/panel.c
WARNING: No kernel-doc for file ../drivers/gpu/drm/bridge/panel.c

Fixes: aa8a8c7e4641 ("drm/bridge: panel: move all code to drm_panel.c")
Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://patch.msgid.link/20260928210326.1526997-1-rdunlap@infradead.org
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

DRM's fbdev helpers are for the fbdev-emulation clients. Move them
into the client-library module. Fix include statements throughout
DRM drivers.

While at it, rename the files from drm_fb_helper to drm_fbdev_helper.
The old name was too reminiscent of DRM's framebuffer code.

The GEM support code for fbdev remains part of DRM's memory managers.

v4:
- fix the depedendencies from v3
v3:
- remove obsolete dependencies from Kconfig
v2:
- update armada und docs

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patch.msgid.link/20260928080323.23909-3-tzimmermann@suse.de

Now that a drm-bridge is embedded into every drm_panel during the panel
creation, the panel_bridge does not really exist anymore. Its API has been
deprecated and kept until drivers convert to the bridge API.

Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://patch.msgid.link/20260916-drm-bridge-every-panel-v3-8-83afb4f1a707@bootlin.com
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

The deprecated devm_drm_put_bridge() function is not used anymore.

Acked-by: Maxime Ripard <mripard@kernel.org>
Link: https://patch.msgid.link/20260916-drm-bridge-every-panel-v3-6-83afb4f1a707@bootlin.com
Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>

Add a kernel-doc DOC section at the top of xe_migrate.c describing the
Ultra Low Latency Submission (ULLS) scheme used for migration jobs.

Cover the motivation (removing the H2G / GuC / context switch latency
from the page fault and SVM prefetch critical paths), the platform
requirements, the LRC PPHWSP semaphore layout and its relationship to
the migration queue job count, the fixed ULLS job size and why it is
needed, the ring preamble / postamble emitted by the ring ops including
the in-ring tail update, the semaphore-only submission fast path in the
GuC backend, and the enter / delayed exit flow along with the ULLS job
flags.

Hook the new section into Documentation/gpu/xe/xe_migrate.rst.

Signed-off-by: Matthew Brost <matthew.brost@intel.com>
Assisted-by: Github-Copilot:Claude-opus-5
Reviewed-by: Maarten Lankhorst <dev@lankhorst.se>
Link: https://patch.msgid.link/20260925201526.1355279-25-matthew.brost@intel.com

FSP, the GPU's Foundation Security Processor, receives the driver's
messages as packets of MCTP, the Management Component Transport
Protocol. It requires header version 1 in bits 3:0 of the MCTP transport
header.

Nova-core left those bits at zero, so every Chain of Trust request and
every Product Reconfiguration Control request that it sent carried an
invalid transport header.

Declare the version field and set it. Declare the destination endpoint
ID field as well. The driver leaves that field at zero.

Assisted-by: LLM
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Reviewed-by: Zhi Wang <zhiw@nvidia.com>
Link: https://patch.msgid.link/20260918010719.1176945-3-jhubbard@nvidia.com
[acourbot: explicitly set deid field]
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>