linux-toradex.git/Documentation, branch v3.12.45

spi: pl022: Specify 'num-cs' property as required in devicetree binding

2015-07-30T12:10:51+00:00

commit ea6055c46eda1e19e02209814955e13f334bbe1b upstream.

Since commit 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data")
the 'num-cs' parameter cannot be passed through platform data when probing
with devicetree. Instead, it's a required devicetree property.

Fix the binding documentation so the property is properly specified.

Fixes: 39a6ac11df65 ("spi/pl022: Devicetree support w/o platform data")
Signed-off-by: Ezequiel Garcia 
Signed-off-by: Mark Brown 
Signed-off-by: Jiri Slaby

hwmon: (k10temp) Add support for F15h M60h

2015-06-02T09:42:53+00:00

commit f89ce2706d8341c921b96e13a00b951a10eed308 upstream.

This patch adds temperature monitoring support for F15h M60h processor.
 - Add new pci device id for the relevant processor
 - The functionality of REG_REPORTED_TEMPERATURE is moved to
   D0F0xBC_xD820_0CA4 [Reported Temperature Control]
   - So, use this to get CUR_TEMP value
   - Since we need an indirect register access, protect this with
     a mutex lock
 - Add Kconfig, Doc entries to indicate support for this processor.

Signed-off-by: Aravind Gopalakrishnan 
Acked-by: Borislav Petkov 
Acked-by: Clemens Ladisch 
[Guenter Roeck: Declare new mutex and function static]
Signed-off-by: Guenter Roeck 

Signed-off-by: Jiri Slaby

hwmon: (k10temp) Add support for AMD F16 M30h processor

2015-06-02T09:42:38+00:00

commit ec0159503ae74aeb834e78366bdf4b9663ca1129 upstream.

Adding new PCI ID to support AMD F16 M30h processor (Mullins).
While at it, modify Kconfig and Doc files to reflect the
support for newer processors

Note: PCI ID for this processor will make it into pci_ids.h
as part of this patch:
http://marc.info/?l=linux-kernel&m=139291362126057&w=2
which should be pulled into 3.15 when merge window opens
(It currently sits in 'for-next' branch of bp.git-
https://git.kernel.org/cgit/linux/kernel/git/bp/bp.git/log/?h=for-next)

Signed-off-by: Aravind Gopalakrishnan 
Signed-off-by: Guenter Roeck 
Signed-off-by: Jiri Slaby

ARM: dts: imx28: Fix AUART4 TX-DMA interrupt name

2015-05-16T07:12:44+00:00

commit 4ada77e37a773168fea484899201e272ab44ba8b upstream.

Fix a typo in the TX DMA interrupt name for AUART4.
This patch makes AUART4 operational again.

Signed-off-by: Marek Vasut 
Fixes: f30fb03d4d3a ("ARM: dts: add generic DMA device tree binding for mxs-dma")
Acked-by: Stefan Wahren 
Signed-off-by: Shawn Guo 
Signed-off-by: Jiri Slaby

arm/arm64: KVM: Correct KVM_ARM_VCPU_INIT power off option

2015-04-30T09:15:12+00:00

commit 3ad8b3de526a76fbe9466b366059e4958957b88f upstream.

The implementation of KVM_ARM_VCPU_INIT is currently not doing what
userspace expects, namely making sure that a vcpu which may have been
turned off using PSCI is returned to its initial state, which would be
powered on if userspace does not set the KVM_ARM_VCPU_POWER_OFF flag.

Implement the expected functionality and clarify the ABI.

Acked-by: Marc Zyngier 
Signed-off-by: Christoffer Dall 
Signed-off-by: Shannon Zhao 
Signed-off-by: Jiri Slaby

stable_kernel_rules: Add pointer to netdev-FAQ for network patches

2015-04-09T12:13:30+00:00

commit b76fc285337b6b256e9ba20a40cfd043f70c27af upstream.

Stable_kernel_rules should point submitters of network stable patches to the
netdev_FAQ.txt as requests for stable network patches should go to netdev
first.

Signed-off-by: Dave Chiluk 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Jiri Slaby

Input: i8042 - reset keyboard to fix Elantech touchpad detection

2015-01-29T14:44:42+00:00

commit 148e9a711e034e06310a8c36b64957934ebe30f2 upstream.

On some laptops, keyboard needs to be reset in order to successfully detect
touchpad (e.g., some Gigabyte laptop models with Elantech touchpads).
Without resettin keyboard touchpad pretends to be completely dead.

Based on the original patch by Mateusz Jończyk this version has been
expanded to include DMI based detection & application of the fix
automatically on the affected models of laptops. This has been confirmed to
fix problem by three users already on three different models of laptops.

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=81331
Signed-off-by: Srihari Vijayaraghavan 
Acked-by: Mateusz Jończyk 
Tested-by: Srihari Vijayaraghavan 
Tested by: Zakariya Dehlawi 
Tested-by: Guillaum Bouchard 
Signed-off-by: Dmitry Torokhov 
Signed-off-by: Jiri Slaby

pstore-ram: Allow optional mapping with pgprot_noncached

2015-01-26T13:38:46+00:00

commit 027bc8b08242c59e19356b4b2c189f2d849ab660 upstream.

On some ARMs the memory can be mapped pgprot_noncached() and still
be working for atomic operations. As pointed out by Colin Cross
, in some cases you do want to use
pgprot_noncached() if the SoC supports it to see a debug printk
just before a write hanging the system.

On ARMs, the atomic operations on strongly ordered memory are
implementation defined. So let's provide an optional kernel parameter
for configuring pgprot_noncached(), and use pgprot_writecombine() by
default.

Cc: Arnd Bergmann 
Cc: Rob Herring 
Cc: Randy Dunlap 
Cc: Anton Vorontsov 
Cc: Colin Cross 
Cc: Olof Johansson 
Cc: Russell King 
Acked-by: Kees Cook 
Signed-off-by: Tony Lindgren 
Signed-off-by: Tony Luck 
Signed-off-by: Jiri Slaby

Documentation: lzo: document part of the encoding

2014-10-31T14:11:17+00:00

commit d98a0526434d27e261f622cf9d2e0028b5ff1a00 upstream.

Add a complete description of the LZO format as processed by the
decompressor. I have not found a public specification of this format
hence this analysis, which will be used to better understand the code.

Cc: Willem Pinckaers 
Cc: "Don A. Bailey" 
Signed-off-by: Willy Tarreau 
Signed-off-by: Jiri Slaby

kvm: fix potentially corrupt mmio cache

2014-10-31T14:11:08+00:00

commit ee3d1570b58677885b4552bce8217fda7b226a68 upstream.

vcpu exits and memslot mutations can run concurrently as long as the
vcpu does not aquire the slots mutex. Thus it is theoretically possible
for memslots to change underneath a vcpu that is handling an exit.

If we increment the memslot generation number again after
synchronize_srcu_expedited(), vcpus can safely cache memslot generation
without maintaining a single rcu_dereference through an entire vm exit.
And much of the x86/kvm code does not maintain a single rcu_dereference
of the current memslots during each exit.

We can prevent the following case:

   vcpu (CPU 0)                             | thread (CPU 1)
--------------------------------------------+--------------------------
1  vm exit                                  |
2  srcu_read_unlock(&kvm->srcu)             |
3  decide to cache something based on       |
     old memslots                           |
4                                           | change memslots
                                            | (increments generation)
5                                           | synchronize_srcu(&kvm->srcu);
6  retrieve generation # from new memslots  |
7  tag cache with new memslot generation    |
8  srcu_read_unlock(&kvm->srcu)             |
...                                         |
                       |
...                                         |
                                  |
                                            |

By incrementing the generation after synchronizing with kvm->srcu readers,
we ensure that the generation retrieved in (6) will become invalid soon
after (8).

Keeping the existing increment is not strictly necessary, but we
do keep it and just move it for consistency from update_memslots to
install_new_memslots.  It invalidates old cached MMIOs immediately,
instead of having to wait for the end of synchronize_srcu_expedited,
which makes the code more clearly correct in case CPU 1 is preempted
right after synchronize_srcu() returns.

To avoid halving the generation space in SPTEs, always presume that the
low bit of the generation is zero when reconstructing a generation number
out of an SPTE.  This effectively disables MMIO caching in SPTEs during
the call to synchronize_srcu_expedited.  Using the low bit this way is
somewhat like a seqcount---where the protected thing is a cache, and
instead of retrying we can simply punt if we observe the low bit to be 1.

Signed-off-by: David Matlack 
Reviewed-by: Xiao Guangrong 
Reviewed-by: David Matlack 
Signed-off-by: Paolo Bonzini 
Signed-off-by: Jiri Slaby