linux-toradex.git/arch/arc/include/asm/arcregs.h, branch v3.10.8

ARC: Boot #2: Verbose Boot reporting / feature verification

2013-02-15T17:46:07+00:00

Signed-off-by: Vineet Gupta

ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem init

2013-02-15T17:45:54+00:00

Signed-off-by: Vineet Gupta 
Acked-by: Arnd Bergmann

ARC: MMU Exception Handling

2013-02-15T17:45:52+00:00

* MMU I-TLB / D-TLB Miss Exceptions
  - Fast Path TLB Refill Handler
  - slowpath TLB creation via do_page_fault() -> update_mmu_cache()
* Duplicate PD Exception Handler

Signed-off-by: Vineet Gupta

ARC: MMU Context Management

2013-02-15T17:45:51+00:00

ARC700 MMU provides for tagging TLB entries with a 8-bit ASID to avoid
having to flush the TLB every task switch.

It also allows for a quick way to invalidate all the TLB entries for
task useful for:
* COW sementics during fork()
* task exit()ing

Signed-off-by: Vineet Gupta

ARC: Cache Flush Management

2013-02-15T17:45:50+00:00

* ARC700 has VIPT L1 Caches
* Caches don't snoop and are not coherent
* Given the PAGE_SIZE and Cache associativity, we don't support aliasing
  D$ configurations (yet), but do allow aliasing I$ configs

Signed-off-by: Vineet Gupta

ARC: Timers/counters/delay management

2013-02-11T14:30:39+00:00

ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1.
Both have exactly same capabilies.

* programmable to count from TIMER_CNT to TIMER_LIMIT
* for count 0 and LIMIT ~1, provides a free-running counter by
    auto-wrapping when limit is reached.
* optionally interrupt when LIMIT is reached (oneshot event semantics)
* rearming the interrupt provides periodic semantics
* run at CPU clk

ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for
clocksource (free-running clock).

Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence
is more apt for clocksource when available.

SMP poses a bit of challenge for global timekeeping clocksource /
sched_clock() backend:
 -TIMER1 based local clocks are out-of-sync hence can't be used
  (thus we default to jiffies based cs as well as sched_clock() one/both
  of which platform can override with it's specific hardware assist)
 -RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue
  ensures that) and thus usable for both requirements.

Signed-off-by: Vineet Gupta 
Cc: Thomas Gleixner

ARC: Process-creation/scheduling/idle-loop

2013-02-11T14:30:38+00:00

Signed-off-by: Vineet Gupta 
Cc: Al Viro 
Cc: Thomas Gleixner

ARC: Interrupt Handling

2013-02-11T14:30:37+00:00

This contains:
-bootup arch IRQ init: init_IRQ(), arc_init_IRQ()
-generic IRQ subsystem glue: arch_do_IRQ()
-basic IRQ chip setup for in-core intc

Signed-off-by: Vineet Gupta 
Cc: Thomas Gleixner

ARC: irqflags - Interrupt enabling/disabling at in-core intc

2013-02-11T14:30:30+00:00

ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels"
of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts.

CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2)
to globally enable (or disable) all IRQs at a level. Hence the
implementation of arch_local_irq_{save,restore,enable,disable}( )

The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence
the use of LR/SR instructions. Further, E1/E2 bits in there can only be
updated using the FLAG insn.

The intc supports 32 interrupts - and per IRQ enabling is controlled by
a bit in the AUX_IENABLE register, hence the implmentation of
arch_{,un}mask_irq( ) routines.

Signed-off-by: Vineet Gupta 
Cc: Thomas Gleixner