linux-toradex.git/arch/arc/include/asm/cache.h, branch v4.2.7

ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)

2015-06-25T00:30:19+00:00

L2 cache on ARCHS processors is called SLC (System Level Cache)
For working DMA (in absence of hardware assisted IO Coherency) we need
to manage SLC explicitly when buffers transition between cpu and
controllers.

Signed-off-by: Vineet Gupta

ARCv2: MMUv4: support aliasing icache config

2015-06-22T08:36:56+00:00

This is also default for AXS103 release

Signed-off-by: Vineet Gupta

ARCv2: MMUv4: cache programming model changes

2015-06-22T08:36:55+00:00

Caveats about cache flush on ARCv2 based cores

- dcache is PIPT so paddr is sufficient for cache maintenance ops (no
  need to setup PTAG reg

- icache is still VIPT but only aliasing configs need PTAG setup

So basically this is departure from MMU-v3 which always need vaddr in
line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG,
IC_PTAG respectively.

Signed-off-by: Vineet Gupta

ARC: Update comments about uncached address space

2014-10-13T09:16:16+00:00

Suggested-by: Noam Camus 
Signed-off-by: Vineet Gupta

ARC: remove checks for CONFIG_ARC_MMU_V4

2014-06-16T06:04:29+00:00

There's no Kconfig symbol ARC_MMU_V4 so the checks for CONFIG_ARC_MMU_V4
will always evaluate to false. Remove them.

Signed-off-by: Paul Bolle 
Signed-off-by: Vineet Gupta

ARC: Disable caches in early boot if so configured

2014-06-03T09:44:48+00:00

Requested-by: Noam Camus 
Signed-off-by: Vineet Gupta

ARC: cacheflush refactor #2: I and D caches lines to have same size

2013-11-06T05:11:37+00:00

Having them be different seems an obscure configuration.

Signed-off-by: Vineet Gupta

ARC: fix new Section mismatches in build (post __cpuinit cleanup)

2013-09-05T13:49:06+00:00

--------------->8--------------------
WARNING: vmlinux.o(.text+0x708): Section mismatch in reference from the
function read_arc_build_cfg_regs() to the function
.init.text:read_decode_cache_bcr()

WARNING: vmlinux.o(.text+0x702): Section mismatch in reference from the
function read_arc_build_cfg_regs() to the function
.init.text:read_decode_mmu_bcr()
--------------->8--------------------

Signed-off-by: Vineet Gupta

ARC: cache detection code bitrot

2013-06-22T08:16:43+00:00

* Number of (i|d)cache ways can be retrieved from BCRs and hence no need
  to cross check with with built-in constants
* Use of IS_ENABLED() to check for a Kconfig option
* is_not_cache_aligned() not used anymore

Signed-off-by: Vineet Gupta

ARC: Disintegrate arcregs.h

2013-06-22T08:16:42+00:00

* Move the various sub-system defines/types into relevant files/functions
  (reduces compilation time)

* move CPU specific stuff out of asm/tlb.h into asm/mmu.h

Signed-off-by: Vineet Gupta