linux-toradex.git/arch/arc/kernel/entry-arcv2.S, branch v5.18

ARC: mm: move MMU specific bits out of entry code ...

2021-08-24T21:25:48+00:00

... to avoid polluting shared entry code (across three ISA variants)
with ISA/MMU specific code.

Cc: Jose Abreu 
Signed-off-by: Vineet Gupta

ARCv2: entry: simplify return to Delay Slot via interrupt

2019-07-08T08:24:45+00:00

Commit 4255b07f2c9c43540 ("ARCv2: STAR 9000793984: Handle return
from intr to Delay Slot") involved a complex 2 staged trampoline.

Apparently this can be greatly simplified by returning from pure
kernel mode (iso interrupt) so drop to pure kernel mdoe and execute
the normal exception return path.

Testing this was a bit of challenge as return from interrupt is rarely
executed now after commit 4de0e52867d83105767 ("ARCv2: STAR 9000814690:
Really Re-enable interrupts to avoid deadlocks"). That fix is necessary
evil and pct interrupts etc do exercise intr return path.
Anyhow after a revert of above in my local test setup I was able to hit
this case and verify the patch works.

Signed-off-by: Vineet Gupta

ARCv2: entry: rewrite to enable use of double load/stores LDD/STD

2019-07-01T18:02:22+00:00

 - the motivation was to be remove blatent copy-paste due to hasty support
   of CONFIG_ARC_IRQ_NO_AUTOSAVE support

 - but with refactoring we could use LDD/STD to greatly optimize the code

Signed-off-by: Vineet Gupta

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55+00:00

Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Enrico Weigelt 
Reviewed-by: Kate Stewart 
Reviewed-by: Allison Randal 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman

ARCv2: support manual regfile save on interrupts

2019-02-21T19:03:18+00:00

There's a hardware bug which affects the HSDK platform, triggered by
micro-ops for auto-saving regfile on taken interrupt. The workaround is
to inhibit autosave.

Signed-off-by: Vineet Gupta

ARCv2: make unimplemented vectors as no-ops rather than halt core

2017-03-21T01:47:57+00:00

Signed-off-by: Vineet Gupta

ARCv2: intc: Rework the build time irq count information

2017-02-06T17:37:57+00:00

Currently Kconfig knob ARC_NUMBER_OF_INTERRUPTS is used as indicator of
hard irq count. But it is flawed that it doesn't affect
 - NR_IRQS     : for number of virtual interrupts
 - NR_CPU_IRQS : for number of hardware interrupts

Moreover the actual hardware irq count might still not be same as
ARC_NUMBER_OF_INTERRUPTS. So use the information availble in the
Build Configuration Registers and get rid of the Kconfig option.

We still need "some" build time info about irq count to set up
sufficient number of vector table entries. This is done with a
sufficiently large NR_CPU_IRQS which will eventually be used soley for
that purpose (subsequent patches will remove its usage elsewhere)

So to summarize what this patch does:

  * NR_CPU_IRQS defines a maximum number of hardware interrupts.
  * Remove ARC_NUMBER_OF_INTERRUPTS option and create interrupts
    table for all possible hardware interrupts.
  * Increase a maximum number of virtual IRQs to 512. ARCv2 can
    support 240 interrupts in the core interrupts controllers
    and 128 interrupts in IDU. Thus 512 virtual IRQs must be
    enough for most configurations of boards.

This patch leads to NR_CPU_IRQS in 2 places, to reduce the overall
churn. The next patch will remove the 2nd definition anyways.

Signed-off-by: Yuriy Kolerov 
Signed-off-by: Vineet Gupta 
[vgupta: reworked the changelog a bit]

ARCv2: entry: document intr disable in hard isr

2016-12-14T17:23:45+00:00

And while at it - use the proper assembler macro which includes the
optional irq tracing already - de-uglify'ing the code a bit

Signed-off-by: Vineet Gupta

ARCv2: Enable LOCKDEP

2016-04-22T12:42:31+00:00

- The asm helpers for calling into irq tracer were missing

- Add calls to above helpers in low level assembly entry code for ARCv2

- irq_save() uses CLRI to disable interrupts and returns the prev interrupt
  state (in STATUS32) in a specific encoding (and not the raw value of
  STATUS32). This is usable with SETI in irq_restore(). However
  save_flags() reads the raw value of STATUS32 which doesn't pair with
  irq_save/restore() and thus needs fixing.

Signed-off-by: Evgeny Voevodin 
[vgupta: updated changelog and also added some comments]
Signed-off-by: Vineet Gupta

ARCv2: SMP: Emulate IPI to self using software triggered interrupt

2016-02-24T05:37:28+00:00

ARConnect/MCIP Inter-Core-Interrupt module can't send interrupt to
local core. So use core intc capability to trigger software
interrupt to self, using an unsued IRQ #21.

This showed up as csd deadlock with LTP trace_sched on a dual core
system. This test acts as scheduler fuzzer, triggering all sorts of
schedulting activity. Trouble starts with IPI to self, which doesn't get
delivered (effectively lost due to H/w capability), but the msg intended
to be sent remain enqueued in per-cpu @ipi_data.

All subsequent IPIs to this core from other cores get elided due to the
IPI coalescing optimization in ipi_send_msg_one() where a pending msg
implies an IPI already sent and assumes other core is yet to ack it.
After the elided IPI, other core simply goes into csd_lock_wait()
but never comes out as this core never sees the interrupt.

Fixes STAR 9001008624

Cc: Peter Zijlstra 
Cc:         [4.2]
Signed-off-by: Vineet Gupta