linux-toradex.git/arch/arc, branch v4.14-rc4

ARC: [plat-hsdk]: Add reset controller node to manage ethernet reset

2017-10-06T15:59:54+00:00

DW ethernet controller on HSDK hangs sometimes after SW reset, so
add reset node to make possible to reset DW ethernet controller HW.

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta

ARC: [plat-hsdk]: Temporary fix to set CPU frequency to 1GHz

2017-10-04T03:36:49+00:00

Add temporary fix to HSDK platform code to setup CPU frequency
to 1GHz on early boot.
We can remove this fix when smart hsdk pll driver will be
introduced, see discussion:
https://www.mail-archive.com/linux-snps-arc@lists.infradead.org/msg02689.html

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta

ARC: fix allnoconfig build warning

2017-10-04T03:36:49+00:00

Reported-by: Dmitrii Kolesnichenko 
Signed-off-by: Vineet Gupta

ARCv2: boot log: identify HS48 cores (dual issue)

2017-10-04T03:36:49+00:00

Signed-off-by: Vineet Gupta

ARC: boot log: decontaminate ARCv2 ISA_CONFIG register

2017-10-04T03:36:49+00:00

ARCv2 ISA_CONFIG and ARC700_BUILD build config registers are not
compatible. cpuinfo_arc had isa info placeholder which was mashup of bits
form both.

Untangle this by defining it off of ARCv2 ISA info and it is fine even
for ARC700 since former is a super set of latter (ARC700 buildonly has 2
bits for atomics and stack check).

At runtime, we treat ARCv2 ISA info as a generic placeholder but
populate it correctly depending on ARC700 or HS.

This paves way for adding more HS specific bits in isa info which was
colliding with the extra bits for arc700.

Signed-off-by: Vineet Gupta

arc: remove redundant UTS_MACHINE define in arch/arc/Makefile

2017-10-04T03:36:49+00:00

The top-level Makefile sets the default of UTS_MACHINE to $(ARCH).

If ARCH and UTS_MACHINE match, arch/$(ARCH)/Makefile need not specify
UTS_MACHINE explicitly.

Signed-off-by: Masahiro Yamada 
Signed-off-by: Vineet Gupta

ARC: [plat-hsdk] use actual clk driver to manage cpu clk

2017-10-04T03:36:49+00:00

With corresponding clk driver now merged upstream, switch to it.

 - core_clk now represent the PLL (vs. fixed clk before)
 - input_clk represent the clk signal src for PLL (basically xtal)

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta

ARC: [*defconfig] Reenable soft lock-up detector

2017-10-04T03:36:49+00:00

Commit 92e5aae45778 "kernel/watchdog: split up config options"
introduced SOFTLOCKUP_DETECTOR which selects LOCKUP_DETECTOR
instead of the latter to be selected itself.

We need to adjust our defconfigs accordingly.

Signed-off-by: Alexey Brodkin 
Signed-off-by: Vineet Gupta

ARC: [plat-axs10x] sdio: Temporary fix of sdio ciu frequency

2017-10-04T03:36:49+00:00

DW sdio controller has external ciu clock divider controlled
via register in SDIO IP. It divides sdio_ref_clk
(which comes from CGU) by 16 for default. So default mmcclk
clock (which comes to sdk_in) is 25000000 Hz.

So fix wrong current value (50000000 Hz) to actual 25000000 Hz.

Note this is a preventive fix, in line with similar change for HSDK
where this was actually needed. see:
http://lists.infradead.org/pipermail/linux-snps-arc/2017-September/002924.html

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta

ARC: [plat-hsdk] sdio: Temporary fix of sdio ciu frequency

2017-10-04T03:36:49+00:00

DW sdio controller has external ciu clock divider controlled via
register in SDIO IP. Due to its unexpected default value
(it should divide by 1 but it divides by 8)
SDIO IP uses wrong ciu clock and works unstable

So add temporary fix and change clock frequency from 100000000
to 12500000 Hz until we fix dw sdio driver itself.

Fixes SNPS STAR 9001204800

Signed-off-by: Eugeniy Paltsev 
Signed-off-by: Vineet Gupta