linux-toradex.git/arch/arm/Kconfig-nommu, branch v3.10.32 Linux kernel for Apalis and Colibri modules Fix common misspellings 2011-03-31T14:26:23+00:00 Lucas De Marchi lucas.demarchi@profusion.mobi 2011-03-31T01:57:33+00:00 25985edcedea6396277003854657b5f3cb31a628 Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi> 
Fixes generated by 'codespell' and manually reviewed.

Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
[ARM] 4532/1: allow configuration of processor ID 2007-10-12T22:43:02+00:00 Greg Ungerer gerg@snapgear.com 2007-07-30T01:26:08+00:00 7a8be08b1be0bb2a973787bdf888e0a4177cdcd8 Allow for configuration of the processor ID for the simplar non-MMU ARM parts. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Allow for configuration of the processor ID for the simplar non-MMU
ARM parts.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] nommu: manage the CP15 things 2006-09-27T16:34:30+00:00 Hyok S. Choi hyok.choi@samsung.com 2006-09-26T08:36:37+00:00 f12d0d7c7786af39435ef6ae9defe47fb58f6091 All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] nommu: fixups for the exception vectors 2006-03-27T14:18:50+00:00 Hyok S. Choi hyok.choi@samsung.com 2006-03-27T14:18:50+00:00 c760fc1997e8156ebc4134c42c18f68137c689f9 The high page vector (0xFFFF0000) does not supported in nommu mode. This patch allows the vectors to be 0x00000000 or the begining of DRAM in nommu mode. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The high page vector (0xFFFF0000) does not supported in nommu mode.
This patch allows the vectors to be 0x00000000 or the begining of DRAM
in nommu mode.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] nommu: add nommu specific Kconfig and MMUEXT variable in Makefile 2006-03-27T14:14:19+00:00 Hyok S. Choi hyok.choi@samsung.com 2006-03-27T14:14:19+00:00 f8c07de6beac55c3273cbd679bfa67555ef14ef5 This patch adds Kconfig-nommu for noMMU specific configurations and MMUEXT variable into Makefile. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
This patch adds Kconfig-nommu for noMMU specific configurations
and MMUEXT variable into Makefile.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>