<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-toradex.git/arch/arm/common/mcpm_entry.c, branch v4.10</title>
<subtitle>Linux kernel for Apalis and Colibri modules</subtitle>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/'/>
<entry>
<title>ARM: MCPM: remove residency argument from mcpm_cpu_suspend()</title>
<updated>2015-05-06T15:47:10+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2015-04-28T19:51:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7895f73169ade9a74940ae6b0b4ee82faf286861'/>
<id>7895f73169ade9a74940ae6b0b4ee82faf286861</id>
<content type='text'>
This is currently unused.

If a suspend must be limited to CPU level only by preventing the last man
from triggering a cluster level suspend then this should be determined
according to many other criteria the MCPM layer is currently not aware of.
It is unlikely that mcpm_cpu_suspend() would be the proper conduit for
that information anyway.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</content>
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<pre>
This is currently unused.

If a suspend must be limited to CPU level only by preventing the last man
from triggering a cluster level suspend then this should be determined
according to many other criteria the MCPM layer is currently not aware of.
It is unlikely that mcpm_cpu_suspend() would be the proper conduit for
that information anyway.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: MCPM: add references to the available documentation in the code</title>
<updated>2015-05-06T15:46:15+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2015-04-28T18:51:36+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1c2c7d51c8101ab3c5d8585713d2dcd52d77d33e'/>
<id>1c2c7d51c8101ab3c5d8585713d2dcd52d77d33e</id>
<content type='text'>
Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: MCPM: make internal helpers private to the core code</title>
<updated>2015-05-06T15:45:46+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2015-04-28T18:11:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=7cc8b991cdc985aaa73bf9c429c810cd442fb74d'/>
<id>7cc8b991cdc985aaa73bf9c429c810cd442fb74d</id>
<content type='text'>
This concerns the following helpers:

	__mcpm_cpu_going_down()
	__mcpm_cpu_down()
	__mcpm_outbound_enter_critical()
	__mcpm_outbound_leave_critical()
	__mcpm_cluster_state()

They are and should only be used by the core code now.  Therefore their
declarations are removed from mcpm.h and their definitions are made
static, hence the need to move them before their users which accounts
for the bulk of this patch.

This left the mcpm_sync_struct definition at an odd location, therefore
it is moved as well with some comment clarifications.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</content>
<content type='xhtml'>
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<pre>
This concerns the following helpers:

	__mcpm_cpu_going_down()
	__mcpm_cpu_down()
	__mcpm_outbound_enter_critical()
	__mcpm_outbound_leave_critical()
	__mcpm_cluster_state()

They are and should only be used by the core code now.  Therefore their
declarations are removed from mcpm.h and their definitions are made
static, hence the need to move them before their users which accounts
for the bulk of this patch.

This left the mcpm_sync_struct definition at an odd location, therefore
it is moved as well with some comment clarifications.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: MCPM: remove backward compatibility code</title>
<updated>2015-05-06T15:43:12+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2015-04-28T17:44:00+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=77404d81cadf192cc1261d6269f622a06b83cdd5'/>
<id>77404d81cadf192cc1261d6269f622a06b83cdd5</id>
<content type='text'>
Now that no one uses the old callbacks anymore, let's remove them
and associated support code.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Now that no one uses the old callbacks anymore, let's remove them
and associated support code.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: MCPM: move the algorithmic complexity to the core code</title>
<updated>2015-04-03T19:52:46+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2015-03-11T22:16:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=d3a875444ad8d5e64c5a932361ca579312e49801'/>
<id>d3a875444ad8d5e64c5a932361ca579312e49801</id>
<content type='text'>
All backends are reimplementing a variation of the same CPU reference
count handling. They are also responsible for driving the MCPM special
low-level locking. This is needless duplication, involving algorithmic
requirements that are not necessarily obvious to the uninitiated.
And from past code review experience, those were all initially
implemented badly.

After 3 years, it is time to refactor as much common code to the core
MCPM facility to make the backends as simple as possible.  To avoid a
flag day, the new scheme is introduced in parallel to the existing
backend interface.  When all backends are converted over, the
compatibility interface could be removed.

The new MCPM backend interface implements simpler methods addressing
very platform specific tasks performed under lock protection while
keeping the algorithmic complexity and race avoidance local to the
core code.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Tested-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
All backends are reimplementing a variation of the same CPU reference
count handling. They are also responsible for driving the MCPM special
low-level locking. This is needless duplication, involving algorithmic
requirements that are not necessarily obvious to the uninitiated.
And from past code review experience, those were all initially
implemented badly.

After 3 years, it is time to refactor as much common code to the core
MCPM facility to make the backends as simple as possible.  To avoid a
flag day, the new scheme is introduced in parallel to the existing
backend interface.  When all backends are converted over, the
compatibility interface could be removed.

The new MCPM backend interface implements simpler methods addressing
very platform specific tasks performed under lock protection while
keeping the algorithmic complexity and race avoidance local to the
core code.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Tested-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 8081/1: MCPM: provide infrastructure to allow for MCPM loopback</title>
<updated>2014-07-18T10:58:00+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2014-06-24T17:32:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=3721924c81541d828d73d0e36dcbae8fd93f0885'/>
<id>3721924c81541d828d73d0e36dcbae8fd93f0885</id>
<content type='text'>
The kernel already has the responsibility to handle resources such as the

CCI when hotplugging CPUs, during the booting of secondary CPUs, and when
resuming from suspend/idle.  It would be more coherent and less confusing
if the CCI for the boot CPU (or cluster)  was also initialized by the
kernel rather than expecting the firmware/bootloader to do it and only in
that case. After all, the kernel has all the necessary code already and
the bootloader shouldn't have to care at all.

The CCI may be turned on only when the cache is off. Leveraging the CPU
suspend code to loop back through the low-level MCPM entry point is all
that is needed to properly turn on the CCI from the kernel by using the
same code as during secondary boot.

Let's provide a generic MCPM loopback function that can be invoked by
backend initialization code to set things (CCI or similar) on the boot
CPU just as it is done for the other CPUs.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Reviewed-by: Kevin Hilman &lt;khilman@linaro.org&gt;
Tested-by: Kevin Hilman &lt;khilman@linaro.org&gt;
Tested-by: Doug Anderson &lt;dianders@chromium.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The kernel already has the responsibility to handle resources such as the

CCI when hotplugging CPUs, during the booting of secondary CPUs, and when
resuming from suspend/idle.  It would be more coherent and less confusing
if the CCI for the boot CPU (or cluster)  was also initialized by the
kernel rather than expecting the firmware/bootloader to do it and only in
that case. After all, the kernel has all the necessary code already and
the bootloader shouldn't have to care at all.

The CCI may be turned on only when the cache is off. Leveraging the CPU
suspend code to loop back through the low-level MCPM entry point is all
that is needed to properly turn on the CCI from the kernel by using the
same code as during secondary boot.

Let's provide a generic MCPM loopback function that can be invoked by
backend initialization code to set things (CCI or similar) on the boot
CPU just as it is done for the other CPUs.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Reviewed-by: Kevin Hilman &lt;khilman@linaro.org&gt;
Tested-by: Kevin Hilman &lt;khilman@linaro.org&gt;
Tested-by: Doug Anderson &lt;dianders@chromium.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge branches 'alignment', 'fixes', 'l2c' (early part) and 'misc' into for-next</title>
<updated>2014-06-05T11:35:52+00:00</updated>
<author>
<name>Russell King</name>
<email>rmk+kernel@arm.linux.org.uk</email>
</author>
<published>2014-06-05T11:35:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=1fb333489fb917c704ad43e51b45c12f52215a9c'/>
<id>1fb333489fb917c704ad43e51b45c12f52215a9c</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 8029/1: mcpm: Rename the power_down_finish() functions to be less confusing</title>
<updated>2014-05-25T22:48:12+00:00</updated>
<author>
<name>Dave Martin</name>
<email>Dave.Martin@arm.com</email>
</author>
<published>2014-04-17T15:58:39+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=166aaf396654b533f536f2cf84d7558eb42f1c9f'/>
<id>166aaf396654b533f536f2cf84d7558eb42f1c9f</id>
<content type='text'>
The name "power_down_finish" seems to be causing some confusion,
because it suggests that this function is responsible for taking
some action to cause the specified CPU to complete its power down.

This patch renames the affected functions to "wait_for_powerdown"
and similar, since this function's intended purpose is just to wait
for the hardware to finish a powerdown initiated by a previous
cpu_power_down.

Signed-off-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The name "power_down_finish" seems to be causing some confusion,
because it suggests that this function is responsible for taking
some action to cause the specified CPU to complete its power down.

This patch renames the affected functions to "wait_for_powerdown"
and similar, since this function's intended purpose is just to wait
for the hardware to finish a powerdown initiated by a previous
cpu_power_down.

Signed-off-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 8032/1: bL_switcher: fix validation check before its activation</title>
<updated>2014-04-22T21:23:59+00:00</updated>
<author>
<name>Nicolas Pitre</name>
<email>nicolas.pitre@linaro.org</email>
</author>
<published>2014-04-21T23:25:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=4530e4b6a450af14973c2b0703edfb02d66cbd41'/>
<id>4530e4b6a450af14973c2b0703edfb02d66cbd41</id>
<content type='text'>
The switcher should not depend on MAX_CLUSTER to determine ifit should
be activated or not. In a multiplatform kernel binary it is possible to
have dual-cluster and quad-cluster platforms configured in. In that case
MAX_CLUSTER which is a build time limit should be 4 and that shouldn't
prevent the switcher from working if the kernel is booted on a b.L
dual-cluster system.

In bL_switcher_halve_cpus() we already have a runtime validation check
to make sure we're dealing with only two clusters, so booting on a quad
cluster system will be caught and switcher activation aborted.

However, the b.L switcher must ensure the MCPM layer is initialized on
the booted hardware before doing anything.  The mcpm_is_available()
function is added to that effect.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Tested-by: Abhilash Kesavan &lt;kesavan.abhilash@gmail.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The switcher should not depend on MAX_CLUSTER to determine ifit should
be activated or not. In a multiplatform kernel binary it is possible to
have dual-cluster and quad-cluster platforms configured in. In that case
MAX_CLUSTER which is a build time limit should be 4 and that shouldn't
prevent the switcher from working if the kernel is booted on a b.L
dual-cluster system.

In bL_switcher_halve_cpus() we already have a runtime validation check
to make sure we're dealing with only two clusters, so booting on a quad
cluster system will be caught and switcher activation aborted.

However, the b.L switcher must ensure the MCPM layer is initialized on
the booted hardware before doing anything.  The mcpm_is_available()
function is added to that effect.

Signed-off-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Tested-by: Abhilash Kesavan &lt;kesavan.abhilash@gmail.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>ARM: 7921/1: mcpm: remove redundant dsb instructions prior to sev</title>
<updated>2013-12-29T12:32:44+00:00</updated>
<author>
<name>Will Deacon</name>
<email>will.deacon@arm.com</email>
</author>
<published>2013-12-10T19:12:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.toradex.cn/cgit/linux-toradex.git/commit/?id=03aa6580e336c19e923372a3b6b72a300f24880c'/>
<id>03aa6580e336c19e923372a3b6b72a300f24880c</id>
<content type='text'>
sync_cache_w already includes a dsb, so we can just use sev() directly
then following a cache-sync.

Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
sync_cache_w already includes a dsb, so we can just use sev() directly
then following a cache-sync.

Acked-by: Dave Martin &lt;Dave.Martin@arm.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Russell King &lt;rmk+kernel@arm.linux.org.uk&gt;
</pre>
</div>
</content>
</entry>
</feed>
