linux-toradex.git/arch/arm/include/asm/hardware/cache-uniphier.h, branch v4.9.51 Linux kernel for Apalis and Colibri modules ARM: uniphier: remove SoC-specific SMP code 2016-08-28T16:57:14+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2016-08-10T11:00:48+00:00 dd34b115666a1ccc69e3af52cc92c7410490f4fd The UniPhier architecture (32bit) switched over to PSCI. Remove the SoC-specific SMP operations. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> 
The UniPhier architecture (32bit) switched over to PSCI.  Remove
the SoC-specific SMP operations.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
ARM: uniphier: add outer cache support 2015-10-27T00:20:50+00:00 Masahiro Yamada yamada.masahiro@socionext.com 2015-10-02T04:42:19+00:00 e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 This commit adds support for UniPhier outer cache controller. All the UniPhier SoCs are equipped with the L2 cache, while the L3 cache is currently only integrated on PH1-Pro5 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Olof Johansson <olof@lixom.net> 
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>