linux-toradex.git/arch/arm/include/asm/hardware/gic.h, branch v3.4.52

irq_domain: Remove 'new' irq_domain in favour of the ppc one

2012-02-16T13:11:23+00:00

This patch removes the simplistic implementation of irq_domains and enables
the powerpc infrastructure for all irq_domain users.  The powerpc
infrastructure includes support for complex mappings between Linux and
hardware irq numbers, and can manage allocation of irq_descs.

This patch also converts the few users of irq_domain_add()/irq_domain_del()
to call irq_domain_add_legacy() instead.

v3: Fix bug that set up too many irqs in translation range.
v2: Fix removal of irq_alloc_descs() call in gic driver

Signed-off-by: Grant Likely 
Cc: Rob Herring 
Cc: Benjamin Herrenschmidt 
Cc: Thomas Gleixner 
Cc: Milton Miller 
Tested-by: Olof Johansson

ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

2011-11-15T18:14:02+00:00

Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.

Signed-off-by: Marc Zyngier

ARM: GIC: Add global gic_handle_irq() function

2011-11-15T18:13:05+00:00

Provide the GIC code with a low level handler that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER.

Signed-off-by: Marc Zyngier

ARM: gic: allow GIC to support non-banked setups

2011-11-15T18:13:03+00:00

The GIC support code is heavily using the fact that hardware
implementations are exposing banked registers. Unfortunately, it
looks like at least one GIC implementation (EXYNOS) offers both
the distributor and the CPU interfaces at different addresses,
depending on the CPU.

This problem is solved by allowing the distributor and CPU interface
addresses to be per-cpu variables for the platforms that require it.
The EXYNOS code is updated not to mess with the GIC internals while
handling interrupts, and struct gic_chip_data is back to being private.
The DT binding for the gic is updated to allow an optional "cpu-offset"
value, which is used to compute the various base addresses.

Finally, a new config option (GIC_NON_BANKED) is used to control this
feature, so the overhead is only present on kernels compiled with
support for EXYNOS.

Tested on Origen (EXYNOS4) and Panda (OMAP4).

Cc: Kukjin Kim 
Cc: Will Deacon 
Cc: Thomas Abraham 
Acked-by: Rob Herring 
Signed-off-by: Marc Zyngier

ARM: gic: fix irq_alloc_descs handling for sparse irq

2011-10-31T13:03:27+00:00

Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ
on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or
mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused
irq_alloc_descs to allocate irq_descs after the pre-allocated space.

Make irq_alloc_descs search for an exact irq range and assume it has
been pre-allocated on failure. For DT probing dynamic allocation is used.
DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all
irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is
enabled.

gic_init irq_start param is changed to be signed with negative meaning do
dynamic Linux irq assigment.

Signed-off-by: Rob Herring

ARM: gic: add OF based initialization

2011-10-31T13:03:26+00:00

This adds ARM gic interrupt controller initialization using device tree
data.

The initialization function is intended to be called by of_irq_init
function like this:

const static struct of_device_id irq_match[] = {
	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
	{}
};

static void __init init_irqs(void)
{
	of_irq_init(irq_match);
}

Signed-off-by: Rob Herring 
Reviewed-by: Jamie Iles 
Tested-by: Thomas Abraham 
Acked-by: Grant Likely

ARM: gic: add irq_domain support

2011-10-31T13:03:24+00:00

Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.

The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.

Signed-off-by: Rob Herring 
Cc: Marc Zyngier 
Reviewed-by: Jamie Iles 
Tested-by: Thomas Abraham 
Acked-by: Grant Likely

Merge branch 'ppi-irq-core-for-rmk' of git://github.com/mzyngier/arm-platforms into devel-stable

2011-10-23T13:42:30+00:00

ARM: gic, local timers: use the request_percpu_irq() interface

2011-10-23T12:32:33+00:00

This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).

PPIs are now useable for more than just the local timers.

Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).

Cc: David Brown 
Cc: Thomas Gleixner 
Acked-by: David Brown 
Tested-by: David Brown 
Tested-by: Shawn Guo 
Signed-off-by: Marc Zyngier

ARM: gic: Use cpu pm notifiers to save gic state

2011-09-23T06:35:30+00:00

When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.

This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.

Original-author: Gary King 
Signed-off-by: Colin Cross 
Signed-off-by: Santosh Shilimkar 
Tested-and-Acked-by: Shawn Guo 
Tested-by: Vishwanath BS