linux-toradex.git/arch/arm/include/asm/mmu_context.h, branch v3.4.18 Linux kernel for Apalis and Colibri modules ARM: 7294/1: vectors: use gate_vma for vectors user mapping 2012-03-24T09:38:51+00:00 Will Deacon will.deacon@arm.com 2012-01-20T11:01:13+00:00 f9d4861fc32b995b1616775614459b8f266c803c The current user mapping for the vectors page is inserted as a `horrible hack vma' into each task via arch_setup_additional_pages. This causes problems with the MM subsystem and vm_normal_page, as described here: https://lkml.org/lkml/2012/1/14/55 Following the suggestion from Hugh in the above thread, this patch uses the gate_vma for the vectors user mapping, therefore consolidating the horrible hack VMAs into one. Acked-and-Tested-by: Nicolas Pitre <nico@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The current user mapping for the vectors page is inserted as a `horrible
hack vma' into each task via arch_setup_additional_pages. This causes
problems with the MM subsystem and vm_normal_page, as described here:

https://lkml.org/lkml/2012/1/14/55

Following the suggestion from Hugh in the above thread, this patch uses
the gate_vma for the vectors user mapping, therefore consolidating
the horrible hack VMAs into one.

Acked-and-Tested-by: Nicolas Pitre <nico@linaro.org>

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: add a vma entry for the user accessible vector page 2010-10-02T02:35:19+00:00 Nicolas Pitre nico@fluxnic.net 2010-08-27T03:10:50+00:00 ec706dab290c486837d4a825870ab052bf200279 The kernel makes the high vector page visible to user space. This page contains (amongst others) small code segments that can be executed in user space. Make this page visible through ptrace and /proc/<pid>/mem in order to let gdb perform code parsing needed for proper unwinding. For example, the ERESTART_RESTARTBLOCK handler actually has a stack frame -- it returns to a PC value stored on the user's stack. To unwind after a "sleep" system call was interrupted twice, GDB would have to recognize this situation and understand that stack frame layout -- which it currently cannot do. We could fix this by hard-coding addresses in the vector page range into GDB, but that isn't really portable as not all of those addresses are guaranteed to remain stable across kernel releases. And having the gdb process make an exception for this page and get content from its own address space for it looks strange, and it is not future proof either. Being located above PAGE_OFFSET, this vma cannot be deleted by user space code. Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org> 
The kernel makes the high vector page visible to user space. This page
contains (amongst others) small code segments that can be executed in
user space.  Make this page visible through ptrace and /proc/<pid>/mem
in order to let gdb perform code parsing needed for proper unwinding.

For example, the ERESTART_RESTARTBLOCK handler actually has a stack
frame -- it returns to a PC value stored on the user's stack.   To
unwind after a "sleep" system call was interrupted twice, GDB would
have to recognize this situation and understand that stack frame
layout -- which it currently cannot do.

We could fix this by hard-coding addresses in the vector page range into
GDB, but that isn't really portable as not all of those addresses are
guaranteed to remain stable across kernel releases.  And having the gdb
process make an exception for this page and get  content from its own
address space for it looks strange, and it is not future proof either.

Being located above PAGE_OFFSET, this vma cannot be deleted by
user space code.

Signed-off-by: Nicolas Pitre <nicolas.pitre@linaro.org>
ARM: 5905/1: ARM: Global ASID allocation on SMP 2010-02-15T21:39:51+00:00 Catalin Marinas catalin.marinas@arm.com 2010-01-26T18:09:42+00:00 11805bcfa411c816b7c76fc40724be6733c74ffc The current ASID allocation algorithm doesn't ensure the notification of the other CPUs when the ASID rolls over. This may lead to two processes using the same ASID (but different generation) or multiple threads of the same process using different ASIDs. This patch adds the broadcasting of the ASID rollover event to the other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid" during the handling of the broadcast, the ASID numbering now starts at "smp_processor_id() + 1". At rollover, the cpu_last_asid will be set to NR_CPUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The current ASID allocation algorithm doesn't ensure the notification
of the other CPUs when the ASID rolls over. This may lead to two
processes using the same ASID (but different generation) or multiple
threads of the same process using different ASIDs.

This patch adds the broadcasting of the ASID rollover event to the
other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid"
during the handling of the broadcast, the ASID numbering now starts at
"smp_processor_id() + 1". At rollover, the cpu_last_asid will be set
to NR_CPUS.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
cpumask: use mm_cpumask() wrapper: arm 2009-09-24T00:04:49+00:00 Rusty Russell rusty@rustcorp.com.au 2009-09-24T15:34:49+00:00 56f8ba83a52b9f9e3711eff8e54168ac14aa288f Makes code futureproof against the impending change to mm->cpu_vm_mask. It's also a chance to use the new cpumask_ ops which take a pointer (the older ones are deprecated, but there's no hurry for arch code). Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> 
Makes code futureproof against the impending change to mm->cpu_vm_mask.

It's also a chance to use the new cpumask_ ops which take a pointer
(the older ones are deprecated, but there's no hurry for arch code).

Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
nommu: Remove the context.id from asm-offsets.c when !MMU 2009-07-24T11:34:56+00:00 Catalin Marinas catalin.marinas@arm.com 2009-07-24T11:34:56+00:00 9a45f026bb3ba720765d46f62f5c464d3317a8ab There is no MMU context switching on MMU-less systems. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> 
There is no MMU context switching on MMU-less systems.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
[ARM] Remove linux/sched.h from asm/cacheflush.h and asm/uaccess.h 2008-11-29T18:49:55+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2008-11-29T17:35:51+00:00 87c52578bd050ba395b0cae7079b1128abd2422d ... and fix those drivers that were incorrectly relying upon that include. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
... and fix those drivers that were incorrectly relying upon
that include.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] cachetype: move definitions to separate header 2008-09-01T11:06:24+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2008-08-10T17:10:19+00:00 46097c7dd8bfaf9fb86565b6de45ab5a63afdd53 Rather than pollute asm/cacheflush.h with the cache type definitions, move them to asm/cachetype.h, and include this new header where necessary. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Rather than pollute asm/cacheflush.h with the cache type definitions,
move them to asm/cachetype.h, and include this new header where
necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[ARM] move include/asm-arm to arch/arm/include/asm 2008-08-02T20:32:35+00:00 Russell King rmk@dyn-67.arm.linux.org.uk 2008-08-02T09:55:55+00:00 4baa9922430662431231ac637adedddbb0cfb2d7 Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Move platform independent header files to arch/arm/include/asm, leaving
those in asm/arch* and asm/plat* alone.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>