linux-toradex.git/arch/arm/include/asm/tlbflush.h, branch v3.0.63

ARM: tlb: move noMMU tlb_flush() to asm/tlb.h

2011-02-21T19:29:28+00:00

There's no need to noMMU to put tlb_flush() in asm/tlbflush.h - it's
part of the tlb shootdown interface.  Move it to asm/tlb.h instead, as
per x86.

Signed-off-by: Russell King

Merge branches 'at91', 'dcache', 'ftrace', 'hwbpt', 'misc', 'mmci', 's3c', 'st-ux' and 'unwind' into devel

2010-10-18T21:34:25+00:00

ARM: Allow SMP kernels to boot on UP systems

2010-10-04T19:23:36+00:00

UP systems do not implement all the instructions that SMP systems have,
so in order to boot a SMP kernel on a UP system, we need to rewrite
parts of the kernel.

Do this using an 'alternatives' scheme, where the kernel code and data
is modified prior to initialization to replace the SMP instructions,
thereby rendering the problematical code ineffectual.  We use the linker
to generate a list of 32-bit word locations and their replacement values,
and run through these replacements when we detect a UP system.

Signed-off-by: Russell King

ARM: 6380/1: Introduce __sync_icache_dcache() for VIPT caches

2010-09-19T11:17:44+00:00

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the current cache maintenance operations in
update_mmu_cache(). To avoid this, cache maintenance must be handled in
set_pte_at() (similar to IA-64 and PowerPC).

This patch provides a unified VIPT cache handling mechanism and
implements the __sync_icache_dcache() function for ARMv6 onwards
architectures. It is called from set_pte_at() and replaces the
update_mmu_cache(). The latter is still used on VIVT hardware where a
vm_area_struct is required.

Tested-by: Rabin Vincent 
Cc: Nicolas Pitre 
Signed-off-by: Catalin Marinas 
Signed-off-by: Russell King

ARM: 6379/1: Assume new page cache pages have dirty D-cache

2010-09-19T11:17:43+00:00

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Tested-by: Rabin Vincent 
Cc: Nicolas Pitre 
Signed-off-by: Catalin Marinas 
Signed-off-by: Russell King

ARM: 6299/1: errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID

2010-08-10T21:10:54+00:00

On versions of the Cortex-A9 prior to r2p0, performing TLB invalidations by
ASID match can result in the incorrect ASID being broadcast to other CPUs.
As a consequence of this, the targetted TLB entries are not invalidated
across the system.

This workaround changes the TLB flushing routines to invalidate entries
regardless of the ASID.

Cc: 
Tested-by: Rob Clark 
Acked-by: Catalin Marinas 
Signed-off-by: Will Deacon 
Signed-off-by: Russell King

ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMP

2010-05-08T09:44:30+00:00

The standard I-cache Invalidate All (ICIALLU) and Branch Predication
Invalidate All (BPIALL) operations are not automatically broadcast to
the other CPUs in an ARMv7 MP system. The patch adds the Inner Shareable
variants, ICIALLUIS and BPIALLIS, if ARMv7 and SMP.

Signed-off-by: Catalin Marinas 
Signed-off-by: Russell King

MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itself

2010-02-20T16:41:46+00:00

On VIVT ARM, when we have multiple shared mappings of the same file
in the same MM, we need to ensure that we have coherency across all
copies.  We do this via make_coherent() by making the pages
uncacheable.

This used to work fine, until we allowed highmem with highpte - we
now have a page table which is mapped as required, and is not available
for modification via update_mmu_cache().

Ralf Beache suggested getting rid of the PTE value passed to
update_mmu_cache():

  On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables
  to construct a pointer to the pte again.  Passing a pte_t * is much
  more elegant.  Maybe we might even replace the pte argument with the
  pte_t?

Ben Herrenschmidt would also like the pte pointer for PowerPC:

  Passing the ptep in there is exactly what I want.  I want that
  -instead- of the PTE value, because I have issue on some ppc cases,
  for I$/D$ coherency, where set_pte_at() may decide to mask out the
  _PAGE_EXEC.

So, pass in the mapped page table pointer into update_mmu_cache(), and
remove the PTE value, updating all implementations and call sites to
suit.

Includes a fix from Stephen Rothwell:

  sparc: fix fallout from update_mmu_cache API change

  Signed-off-by: Stephen Rothwell 

Acked-by: Benjamin Herrenschmidt 
Signed-off-by: Russell King

ARM: 5763/1: ARM: SMP: Fix the BUG with CONFIG_PREEMPT enabled

2009-10-15T14:45:15+00:00

This patch fixes the BUG: using smp_processor_id() in preemptible
Below is the stripped backtrace.

BUG: using smp_processor_id() in preemptible [00000000] code: init/1
caller is flush_tlb_mm+0x44/0x70
Backtrace:
[] (dump_backtrace+0x0/0x110) from [] (dump_stack+0x18/0x1c)
 r7:00000000 r6:c00234f0 r5:00000001 r4:c7828000
[] (dump_stack+0x0/0x1c) from [] (debug_smp_processor_id+0xc0/0xf0)
[] (debug_smp_processor_id+0x0/0xf0) from [] (flush_tlb_mm+0x44/0x70)
 r7:00000000 r6:c60b41a0 r5:c60b4154 r4:00000001
[] (flush_tlb_mm+0x0/0x70) from [] (dup_mm+0x304/0x38c)
 r5:c1f09058 r4:00000000
[] (dup_mm+0x0/0x38c) from [] (copy_process+0x7b8/0xeb0)
[] (copy_process+0x0/0xeb0) from [] (do_fork+0x15c/0x29c)
[] (do_fork+0x0/0x29c) from [] (sys_clone+0x34/0x3c)
[] (sys_clone+0x0/0x3c) from [] (ret_fast_syscall+0x0/0x2c)

Signed-off-by: Santosh Shilimkar 
Signed-off-by: Russell King

cpumask: use mm_cpumask() wrapper: arm

2009-09-24T00:04:49+00:00

Makes code futureproof against the impending change to mm->cpu_vm_mask.

It's also a chance to use the new cpumask_ ops which take a pointer
(the older ones are deprecated, but there's no hurry for arch code).

Signed-off-by: Rusty Russell