linux-toradex.git/arch/arm/include/asm, branch Rel3 Linux kernel for Apalis and Colibri modules ENGR00181374-1: nfc: add platform support for NFC driver 2012-08-10T10:19:10+00:00 Alison Wang b18965@freescale.com 2012-07-26T08:24:07+00:00 2d99c7ab39b3fafa92da2ec8c956e18f942f2f1b Add platform support for NFC driver. Signed-off-by: Jason Jin <Jason.jin@freescale.com> 
Add platform support for NFC driver.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
ARM: perf: add support for the Cortex-A5 PMU 2012-03-22T19:19:05+00:00 Will Deacon will.deacon@arm.com 2011-06-03T16:40:15+00:00 b0c0d264055323adb23f6bc641eaf108c7617423 This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event backend. Signed-off-by: Will Deacon <will.deacon@arm.com> (cherry picked from commit 0c205cbe20654616e2f8389c0c1ff707d9dccb63) 
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.

Signed-off-by: Will Deacon <will.deacon@arm.com>
(cherry picked from commit 0c205cbe20654616e2f8389c0c1ff707d9dccb63)
ENGR00175824 fix the wrong patch for arch/arm/include/asm/futex.h 2012-03-01T03:06:51+00:00 Huang Shijie b32955@freescale.com 2012-02-29T10:56:16+00:00 73449f5acd9eca36113bcad220feae0dcdd38a6f The patch "1e5fce1 ENGR00139261 [MX6Q]support 8 bit MMC and eMMC DDR mode" reverts the patch "28d5b74 ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op" This patch just re-reverts the patch 1e5fce1. Acked-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com> 
The patch
   "1e5fce1 ENGR00139261 [MX6Q]support 8 bit MMC and eMMC DDR mode"
reverts the patch
   "28d5b74 ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op"

This patch just re-reverts the patch 1e5fce1.

Acked-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
ENGR00156314-2 [mx6q]gic: save/restore mode for suspend/resume 2012-01-09T12:23:42+00:00 Tony Lin tony.lin@freescale.com 2011-09-09T03:45:11+00:00 80882747cd55ecd987337ed6d4c839d7400d2b0a add code to gic.c for common gic state save/restore. Signed-off-by: Tony Lin <tony.lin@freescale.com> 
add code to gic.c for common gic state save/restore.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
ENGR00139261 [MX6Q]support 8 bit MMC and eMMC DDR mode 2012-01-09T12:23:15+00:00 Tony Lin tony.lin@freescale.com 2011-08-11T09:35:20+00:00 1e5fce1587efddbcaac563ede720c5e5bcc9024e enable 8 bit MMC mode according to mmc stack. enable eMMC DDR mode according to mmc stack, but change sdhci a little, since sdhci does not support DDR mode so far. Signed-off-by: Tony Lin <tony.lin@freescale.com> 
enable 8 bit MMC mode according to mmc stack.
enable eMMC DDR mode according to mmc stack, but change
sdhci a little, since sdhci does not support DDR mode so
far.

Signed-off-by: Tony Lin <tony.lin@freescale.com>
ENGR00139229-1 MX6: Bring up i.MX6 sabreauto with Single core 2012-01-09T12:18:24+00:00 Zeng Zhaoming b32542@freescale.com 2011-06-28T01:15:47+00:00 e9fdc59b7b9f57ac8f886779ded5a8a326f7e9e6 MSL code for bring up MX6 sabreauto board with Single core. Merged from testbuild:imx6_bringup branch. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Dong Aisheng <b29396@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Richard Zhao <richard.zhao@freescale.com> Signed-off-by: Zeng Zhaoming <b32542@freescale.com> Merged-by: Zeng Zhaoming <b32542@freescale.com> Reviewed-by: Jason Liu <r64343@freescale.com> Reviewed-by: Frank Li <Frank.Li@freescale.com> 
MSL code for bring up MX6 sabreauto board with Single core.

Merged from testbuild:imx6_bringup branch.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Jason Liu <r64343@freescale.com>
Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Singed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com>
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Anish Trivedi <anish@freescale.com>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
Signed-off-by: Jason Chen <b02280@freescale.com>
Signed-off-by: Lily Zhang <r58066@freescale.com>
Signed-off-by: Sammy He <r62914@freescale.com>
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Terry Lv <r65388@freescale.com>
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Zeng Zhaoming <b32542@freescale.com>

Merged-by: Zeng Zhaoming <b32542@freescale.com>
Reviewed-by: Jason Liu <r64343@freescale.com>
Reviewed-by: Frank Li <Frank.Li@freescale.com>
cache-l2x0: add enable/disable functions 2012-01-09T11:53:39+00:00 Rob Herring r.herring@freescale.com 2010-05-26T19:56:15+00:00 d051452dad1cbd769e7f48fd02fe2b6c4fcdc44c Signed-off-by: Rob Herring <r.herring@freescale.com> 
Signed-off-by: Rob Herring <r.herring@freescale.com>
ARM: 7099/1: futex: preserve oldval in SMP __futex_atomic_op 2011-10-03T18:41:06+00:00 Will Deacon will.deacon@arm.com 2011-09-23T13:34:12+00:00 28d5b74edcc0819cefa66256fd804c8420aff19f commit df77abcafc8dc881b6c9347548651777088e4b27 upstream. The SMP implementation of __futex_atomic_op clobbers oldval with the status flag from the exclusive store. This causes it to always read as zero when performing the FUTEX_OP_CMP_* operation. This patch updates the ARM __futex_atomic_op implementations to take a tmp argument, allowing us to store the strex status flag without overwriting the register containing oldval. Reported-by: Minho Ban <mhban@samsung.com> Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> 
commit df77abcafc8dc881b6c9347548651777088e4b27 upstream.

The SMP implementation of __futex_atomic_op clobbers oldval with the
status flag from the exclusive store. This causes it to always read as
zero when performing the FUTEX_OP_CMP_* operation.

This patch updates the ARM __futex_atomic_op implementations to take a
tmp argument, allowing us to store the strex status flag without
overwriting the register containing oldval.

Reported-by: Minho Ban <mhban@samsung.com>
Reviewed-by: Nicolas Pitre <nicolas.pitre@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
ARM: 7014/1: cache-l2x0: Fix L2 Cache size calculation. 2011-10-03T18:40:03+00:00 Srinivas Kandagatla srinivas.kandagatla@st.com 2011-08-15T09:43:44+00:00 0dbf5d84ecfa51949a4543da9b215ad36e3ac63f commit 43c734be5571a4daad9f0a3e0b3229a1c0049917 upstream. This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits. The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations. It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small) and also prints incorrect cachesize. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> 
commit 43c734be5571a4daad9f0a3e0b3229a1c0049917 upstream.

This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and
PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3
bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits
[19:17] for Way size, however the existing code only uses 2 bits to
get this value. This results in incorrect cachesize calculations.

It also results in performing operations on the whole cache when we
erroneously decide that the range is big enough (due to l2x0_size being
too small) and also prints incorrect cachesize.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
ARM: 6959/1: SMP build fix for entry-macro-multi.S 2011-06-17T10:25:03+00:00 Magnus Damm damm@opensource.se 2011-06-13T05:46:44+00:00 2bc58a6fd76f89052c7f151d78fb2d8b804aacfe The assembly code in entry-macro-multi.S does not build without the include asm/assembler.h in the case of CONFIG_SMP=y. Fixes the rather theoretical SMP build of mach-shmobile/entry-intc.c: arch/arm/include/asm/entry-macro-multi.S: Assembler messages: arch/arm/include/asm/entry-macro-multi.S:20: Error: bad instruction `alt_smp(test_for_ipi r0,r6,r5,lr)' arch/arm/include/asm/entry-macro-multi.S:20: Error: bad instruction `alt_up_b(9997f)' make[1]: *** [arch/arm/mach-shmobile/entry-intc.o] Error 1 make: *** [arch/arm/mach-shmobile] Error 2 make: *** Waiting for unfinished jobs.... Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
The assembly code in entry-macro-multi.S does not build without
the include asm/assembler.h in the case of CONFIG_SMP=y.

Fixes the rather theoretical SMP build of mach-shmobile/entry-intc.c:

arch/arm/include/asm/entry-macro-multi.S: Assembler messages:
arch/arm/include/asm/entry-macro-multi.S:20: Error: bad instruction `alt_smp(test_for_ipi r0,r6,r5,lr)'
arch/arm/include/asm/entry-macro-multi.S:20: Error: bad instruction `alt_up_b(9997f)'
make[1]: *** [arch/arm/mach-shmobile/entry-intc.o] Error 1
make: *** [arch/arm/mach-shmobile] Error 2
make: *** Waiting for unfinished jobs....

Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>